SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The interrupt enable register (IER) can be programmed to enable/disable any interrupt. There are seven types of interrupt in this mode: receiver error, RHR interrupt, THR interrupt, XOFF received and CTS*/RTS* change of state from low to high. Each interrupt can be enabled/disabled individually. There is also a sleep mode enable bit.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0004h |
| UART1 | 0281 0004h |
| UART2 | 0282 0004h |
| UART3 | 0283 0004h |
| UART4 | 0284 0004h |
| UART5 | 0285 0004h |
| UART6 | 0286 0004h |
| WKUP_UART0 | 2B30 0004h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CTS_IT | RTS_IT | XOFF_IT | SLEEP_MODE | MODEM_STS_IT | LINE_STS_IT | THR_IT | RHR_IT |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | R | 0h | |
| 7 | CTS_IT | R/W | 0h | 0 Disables the CTS* interrupt 1 Enables the CTS* interrupt |
| 6 | RTS_IT | R/W | 0h | 0 Disables the RTS* interrupt 1 Enables the RTS* interrupt |
| 5 | XOFF_IT | R/W | 0h | 0 Disables the XOFF interrupt 1 Enables the XOFF interrupt |
| 4 | SLEEP_MODE | R/W | 0h | 0 Disables sleep mode
1 Enables sleep mode (stop baud rate clock
when the module is inactive) |
| 3 | MODEM_STS_IT | R/W | 0h | 0 Disables the modem status register
interrupt
1 Enables the modem status register interrupt |
| 2 | LINE_STS_IT | R/W | 0h | 0 Disables the receiver line status interrupt 1 Enables the receiver line status interrupt |
| 1 | THR_IT | R/W | 0h | 0 Disables the THR interrupt 1 Enables the THR interrupt |
| 0 | RHR_IT | R/W | 0h | 0 Disables the RHR interrupt and time out
interrupt.
1 Enables the RHR interrupt and time out
interrupt. |