SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Counter Compare B Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 0014h |
| EPWM1 | 2301 0014h |
| EPWM2 | 2302 0014h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| CMPB | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CMPB | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:0 | CMPB | R/W | 0h | The value in the active CMPB register is continuously compared to the time-base counter [TBCNT] When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare B" event This event is sent to the action-qualifier where it is qualified and converted it into one or more actions These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers The actions that can be defined in the AQCTLA and AQCTLB registers include the following [a] Do nothing, the event is ignored [b] Clear: Pull the EPWMxA and/or EPWMxB signal low [c] Set: Pull the EPWMxA and/or EPWMxB signal high [d] Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL[SHDWBMODE] bit By default this register is shadowed [a] If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register In this case, the CMPCTL[LOADBMODE] bit field determines which event will load the active register from the shadow register: [b] Before a write, the CMPCTL[SHDWBFULL] bit can be read to determine if the shadow register is currently full [c] If CMPCTL[SHDWBMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware [d] In either mode, the active and shadow registers share the same memory map address |