SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The MDIO clock is based on a divide-down of the interface (CPPI_ICLK) clock. The application software or driver must control the divide-down value.
See the CPSW3_MDIO_CONTROL_REG register for configuring the Clock Divider ([15-0]CLKDIV) value.