SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The WKUP_CLKOUT0 output pin is controlled by the WKUP_CTRL_MMR_CFG0_CLKOUT_CTRL register in the WKUP_CTRL_MMR0 module; for more information about control registers, refer CTRL_MMR Registers. The following diagram shows a block diagram of internal WKUP_CLKOUT0 mux connections.
| WKUP_CTRL_MMR_CFG0_CLKOUT_CTRL(2)[2-0] WKUP_CLKOUT_SEL | WKUP_CLKOUT0_MUX Output Clock Selection(1) |
|---|---|
| 0x0 | 0 |
| 0x1 | LFOSC0_CLKOUT |
| 0x2 | MAIN_PLL0_HSDIV2_CLKOUT |
| 0x3 | MAIN_PLL1_HSDIV2_CLKOUT |
| 0x4 | MAIN_PLL2_HSDIV9_CLKOUT |
| 0x5 | DEVICE_CLKOUT_32K |
| 0x6 | CLK_12M_RC |
| 0x7 | HFOSC0_CLKOUT |