SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This reset is a MAIN domain warm reset that is executed from the SMS. This is an asynchronous reset type (takes effect immediately). This SMS reset of the Main domain is enabled only when the SMS_COLD_RESET_EN_z bit in WKUP domain CTRLMMR is '0'.
This reset behavior is same as the RESETz_REQ reset signal (RESET_REQz HW Pin) with the exception that it takes effect immediately without need for any reset isolation sequence.
When the domain is configured to operate independently, the domain is configured as a safety domain, and the domain is reset isolated from Main domain resets.
Top Level IOs are not affected.
When the domain is not configured as independent then, this reset will also warm reset the domain.
This is a MAIN domain asynchronous warm reset. Propagates immediately without any reset isolation sequence.
All modules in MAIN domain are reset except CTRLMMR register bits which are reset only on PORz.
IOs are not affected.
All processor cores are reset.
Reason for this reset is captured in CTRLMMR reset status register.