SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Implementation-defined ASIC control, value written to the register is output on asicctl[7 : 0].
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 3144h |
| C7X256V0_DEBUG | 0007 3400 A144h |
| C7X256V0_DEBUG | 0007 3400 B144h |
| C7X256V1_DEBUG | 0007 3800 3144h |
| C7X256V1_DEBUG | 0007 3800 A144h |
| C7X256V1_DEBUG | 0007 3800 B144h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ASICCTL | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED | NONE | 0h | Reserved |
| 7:0 | ASICCTL | R/W | 0h | Implementation-defined ASIC control, value written to the register is output on asicctl[7 : 0]. If external multiplexing of trigger signals is implemented then the number of multiplexed signals on each trigger must be reflected within the Device ID Register. This is done within a Verilog define EXTMUXNUM. |