SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Event clear reg
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| Instance Name | Physical Address |
|---|---|
| C7X256V1_CLEC | 7D28 0008h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ECR_PFLAG | ECR_FLAG | |||||
| W | W | W | |||||
| 0h | 0h | 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:2 | RESERVED | W | 0h | Reserved |
| 1 | ECR_PFLAG | W | 0h | ECR.EDR_Clear - clears EDR flag bit when 2 is written Reset Source: mod_g_rst_n |
| 0 | ECR_FLAG | W | 0h | ECR.EFR_Clear - clears EFR flag bit when 1 is written, also clears corresponding SOC level event if sent to system on SOCinterrupt port Reset Source: mod_g_rst_n |