SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the hardware configuration options
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C14Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| GHWPARAMS3_31 | GHWPARAMS3_30_23 | ||||||
| R | R | ||||||
| 0h | 20h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| GHWPARAMS3_30_23 | GHWPARAMS3_22_18 | GHWPARAMS3_17_12 | |||||
| R | R | R | |||||
| 20h | 10h | 20h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| GHWPARAMS3_17_12 | GHWPARAMS3_11 | GHWPARAMS3_10 | GHWPARAMS3_9_8 | ||||
| R | R | R | R | ||||
| 20h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GHWPARAMS3_7_6 | GHWPARAMS3_5_4 | GHWPARAMS3_3_2 | GHWPARAMS3_1_0 | ||||
| R | R | R | R | ||||
| 2h | 0h | 1h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | GHWPARAMS3_31 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 30:23 | GHWPARAMS3_30_23 | R | 20h | DWC_USB3_CACHE_TOTAL_XFER_RESOURCES Reset Source: rst_mod_g_rst_n |
| 22:18 | GHWPARAMS3_22_18 | R | 10h | DWC_USB3_NUM_IN_EPS Reset Source: rst_mod_g_rst_n |
| 17:12 | GHWPARAMS3_17_12 | R | 20h | DWC_USB3_NUM_EPS Reset Source: rst_mod_g_rst_n |
| 11 | GHWPARAMS3_11 | R | 0h | DWC_USB3_ULPI_CARKIT Reset Source: rst_mod_g_rst_n |
| 10 | GHWPARAMS3_10 | R | 0h | DWC_USB3_VENDOR_CTL_INTERFACE Reset Source: rst_mod_g_rst_n |
| 9:8 | GHWPARAMS3_9_8 | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 7:6 | GHWPARAMS3_7_6 | R | 2h | DWC_USB3_HSPHY_DWIDTH Reset Source: rst_mod_g_rst_n |
| 5:4 | GHWPARAMS3_5_4 | R | 0h | DWC_USB3_FSPHY_INTERFACE Reset Source: rst_mod_g_rst_n |
| 3:2 | GHWPARAMS3_3_2 | R | 1h | DWC_USB3_HSPHY_INTERFACE Reset Source: rst_mod_g_rst_n |
| 1:0 | GHWPARAMS3_1_0 | R | 0h | DWC_USB3_SSPHY_INTERFACE Reset Source: rst_mod_g_rst_n |