SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Digital Watchdog Control Register
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| Instance Name | Physical Address |
|---|---|
| SMS0_RTI_1 | 4393 5090h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DWDCTRL | |||||||
| R/W | |||||||
| 5312ACEDh | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DWDCTRL | |||||||
| R/W | |||||||
| 5312ACEDh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DWDCTRL | |||||||
| R/W | |||||||
| 5312ACEDh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DWDCTRL | |||||||
| R/W | |||||||
| 5312ACEDh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | DWDCTRL | R/W | 5312ACEDh | User and priviledge mode (read): 0x5312ACED = DWD counter is disabled. This is the default value. 0xA98559DA = DWD counter is enabled Any other value = DWD counter state is unchanged (enabled or disabled) Priviledge mode (write): 0xA98559DA = DWD counter is enabled Any other value = State of DWD counter is unchanged (stays enabled or disabled) Note: One-Write Functionality of DWDCTRL Register The RTIDWDCTRL register implements a one-write functionality, such that the application cannot write to this registermore than once. Writing the default value will not enable the watchdog as described above. Writing the enable value will start the watchdog counters. A write to RTIDWDCTRL will only be enabled after a system reset again. Reset Source: sms_custom_rst_mod_g_rst_n |