SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Controls Relaxed Ordering by OrderID for the C7xv0 L2 Memory from external accesses. Ordering of accesses to the same 4KB L2 Block is relaxed either between Reads (more strict) or Between both Reads and Writes (more relaxed)
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| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 4300h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| C7XV_CTRL0_ORD15 | C7XV_CTRL0_ORD14 | C7XV_CTRL0_ORD13 | C7XV_CTRL0_ORD12 | C7XV_CTRL0_ORD11 | C7XV_CTRL0_ORD10 | C7XV_CTRL0_ORD9 | C7XV_CTRL0_ORD8 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 1h | 1h | 1h | 1h | 1h | 1h |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| C7XV_CTRL0_ORD7 | C7XV_CTRL0_ORD6 | C7XV_CTRL0_ORD5 | C7XV_CTRL0_ORD4 | C7XV_CTRL0_ORD3 | C7XV_CTRL0_ORD2 | C7XV_CTRL0_ORD1 | C7XV_CTRL0_ORD0 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 1h | 1h | 1h | 1h | 1h | 1h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15 | C7XV_CTRL0_ORD15 | R/W | 0h | Ordering Rule for Order ID 15 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 14 | C7XV_CTRL0_ORD14 | R/W | 0h | Ordering Rule for Order ID 14 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 13 | C7XV_CTRL0_ORD13 | R/W | 1h | Ordering Rule for Order ID 13 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 12 | C7XV_CTRL0_ORD12 | R/W | 1h | Ordering Rule for Order ID 12 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 11 | C7XV_CTRL0_ORD11 | R/W | 1h | Ordering Rule for Order ID 11 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 10 | C7XV_CTRL0_ORD10 | R/W | 1h | Ordering Rule for Order ID 10 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 9 | C7XV_CTRL0_ORD9 | R/W | 1h | Ordering Rule for Order ID 9 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 8 | C7XV_CTRL0_ORD8 | R/W | 1h | Ordering Rule for Order ID 8 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 7 | C7XV_CTRL0_ORD7 | R/W | 0h | Ordering Rule for Order ID 7 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 6 | C7XV_CTRL0_ORD6 | R/W | 0h | Ordering Rule for Order ID 6 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 5 | C7XV_CTRL0_ORD5 | R/W | 1h | Ordering Rule for Order ID 5 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 4 | C7XV_CTRL0_ORD4 | R/W | 1h | Ordering Rule for Order ID 4 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 3 | C7XV_CTRL0_ORD3 | R/W | 1h | Ordering Rule for Order ID 3 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 2 | C7XV_CTRL0_ORD2 | R/W | 1h | Ordering Rule for Order ID 2 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 1 | C7XV_CTRL0_ORD1 | R/W | 1h | Ordering Rule for Order ID 1 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |
| 0 | C7XV_CTRL0_ORD0 | R/W | 1h | Ordering Rule for Order ID 0 Field values (others are reserved): 1'b0 - RELAXED_READ 1'b1 - RELAXED_R_TO_W Reset Source: mod_por_rst_n |