SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Ring N Current Index Register can be read by software for debug purposes to determine the current HW read index for the Ring for the channel.
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DMASS0_RINGACC_0 | 4900 0024h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | INDX | ||||||
| NONE | R/NA | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| INDX | |||||||
| R/NA | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INDX | |||||||
| R/NA | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RESERVED | NONE | 0h | Reserved |
| 19:0 | INDX | R/NA | 0h | Current HW owned read index for the ring. This value is initialized to 0 when the ring is set up and will be incremented by HW each time HW processes a ring entry. When the index is incremented to a value equal to the size field in the Ring Size Register for the ring the index will be reset back to 0. Reset Source: srst_n |