SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
Idom0_main_pll_ecc_aggr4 |
IDOM0_MAIN_PLL_ECC_AGGR4_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_168 |
|
IDOM0_MAIN_PLL_ECC_AGGR4_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_169 |
|
|
Idom0_main_pll_ecc_aggr6 |
IDOM0_MAIN_PLL_ECC_AGGR6_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_170 |
|
IDOM0_MAIN_PLL_ECC_AGGR6_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_171 |
|
|
Idom0_pulsar_pll_ecc_aggr8 |
IDOM0_PULSAR_PLL_ECC_AGGR8_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_172 |
|
IDOM0_PULSAR_PLL_ECC_AGGR8_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_173 |
|
|
Idom0_pulsar_pll_ecc_aggr10 |
IDOM0_PULSAR_PLL_ECC_AGGR10_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_174 |
|
IDOM0_PULSAR_PLL_ECC_AGGR10_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_175 |
|
|
Idom1_main_pll_ecc_aggr5 |
IDOM1_MAIN_PLL_ECC_AGGR5_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_176 |
|
IDOM1_MAIN_PLL_ECC_AGGR5_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_177 |
|
|
Idom1_main_pll_ecc_aggr7 |
IDOM1_MAIN_PLL_ECC_AGGR7_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_178 |
|
IDOM1_MAIN_PLL_ECC_AGGR7_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_179 |
|
|
Idom1_pulsar_pll_ecc_aggr9 |
IDOM1_PULSAR_PLL_ECC_AGGR9_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_180 |
|
IDOM1_PULSAR_PLL_ECC_AGGR9_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_181 |
|
|
Idom1_pulsar_pll_ecc_aggr11 |
IDOM1_PULSAR_PLL_ECC_AGGR11_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_182 |
|
IDOM1_PULSAR_PLL_ECC_AGGR11_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_183 |
| OUT Interrupt | Connected To |
|---|---|
|
ADC0_ECC_CORRECTED_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_33 |
|
ADC0_ECC_UNCORRECTED_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_34 |
|
ADC0_FIFO0_PULSE_OUT_0 |
PDMA5_ADC12_0_RX_IN_0 |
|
ADC0_FIFO1_PULSE_OUT_0 |
PDMA5_ADC12_0_RX_IN_1 |
|
ADC0_GEN_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_151 |
|
ADC0_GEN_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_151 |
|
ADC0_GEN_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_151 |
|
ADC0_GEN_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_151 |
|
ADC0_GEN_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_151 |
|
ADC0_GEN_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_151 |
|
ADC0_GEN_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_151 |
| OUT Interrupt | Connected To |
|---|---|
|
DFTSS0_DFT_SAFETY_123_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_98 |
|
DFTSS0_DFT_SAFETY_MULTI_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_99 |
|
DFTSS0_DFT_SAFETY_ONE_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_100 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
WKUP_ECC_AGGR0 |
WKUP_ECC_AGGR0_CORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_23 |
|
WKUP_ECC_AGGR0_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_20 |
|
|
WKUP_ECC_AGGR0_UNCORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_24 |
|
|
WKUP_ECC_AGGR0_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_21 |
|
|
WKUP_ECC_AGGR1 |
WKUP_ECC_AGGR1_CORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_38 |
|
WKUP_ECC_AGGR1_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_104 |
|
|
WKUP_ECC_AGGR1_UNCORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_39 |
|
|
WKUP_ECC_AGGR1_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_105 |
|
|
ECC_AGGR2 |
ECC_AGGR2_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_24 |
|
ECC_AGGR2_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_25 |
|
|
ECC_AGGR3 |
ECC_AGGR3_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_26 |
|
ECC_AGGR3_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_27 |
|
|
ECC_AGGR1 |
ECC_AGGR1_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_2 |
|
ECC_AGGR1_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_1 |
|
|
WKUP_ECC_AGGR2 |
WKUP_ECC_AGGR2_CORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_20 |
|
WKUP_ECC_AGGR2_UNCORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_21 |
|
|
DMASS0_ECC_AGGR_0 |
DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_9 |
|
DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_10 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
am275_main_IPCSS_cbass0 |
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
AM275_MAIN_IPCSS_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
AM275_MAIN_IPCSS_CBASS0_DEFAULT_EXP_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_110 |
|
|
CBASS_MCASP0 |
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
CBASS_MCASP0_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_CENTRAL2 |
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
CBASS_CENTRAL2_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_CENTRAL2 |
CBASS_CENTRAL2_DEFAULT_EXP_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_80 |
|
CBASS_INFRA1 |
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
CBASS_INFRA1_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_INFRA1_DEFAULT_EXP_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_76 |
|
|
CBASS_MEM0 |
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
CBASS_MEM0_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_MEM0_DEFAULT_EXP_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_93 |
|
|
CBASS_MISC_PERI0 |
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
CBASS_MISC_PERI0_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_MISC_PERI0_DEFAULT_EXP_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_5 |
|
|
CBASS0 |
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
CBASS0_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS0_DEFAULT_EXP_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_86 |
|
|
CBASS_DBG0 |
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
CBASS_DBG0_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
WKUP_CBASS0 |
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
WKUP_CBASS0_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
|
|
WKUP_CBASS0_DEFAULT_EXP_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_3 |
|
|
WKUP_CBASS0_DEFAULT_EXP_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_0 |
|
|
WKUP_CBASS_SAFE1 |
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_31 |
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_31 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_31 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_31 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_133 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_133 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_147 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_147 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_147 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_147 |
|
|
WKUP_CBASS_SAFE1_DEFAULT_ERR_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_147 |
| OUT Interrupt | Connected To |
|---|---|
|
MAIN_CTRL_MMR0_IPC_SET0_IPC_SET_IPCFG_OUT_0 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_5 |
|
MAIN_CTRL_MMR0_IPC_SET16_IPC_SET_IPCFG_OUT_0 |
R5FSS0_CORE0_INTR_IN_0 |
|
MAIN_CTRL_MMR0_IPC_SET17_IPC_SET_IPCFG_OUT_0 |
R5FSS0_CORE1_INTR_IN_0 |
|
MAIN_CTRL_MMR0_IPC_SET18_IPC_SET_IPCFG_OUT_0 |
R5FSS1_CORE0_INTR_IN_0 |
|
MAIN_CTRL_MMR0_IPC_SET19_IPC_SET_IPCFG_OUT_0 |
R5FSS1_CORE1_INTR_IN_0 |
|
MAIN_CTRL_MMR0_IPC_SET1_IPC_SET_IPCFG_OUT_0 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_5 |
|
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_129 |
|
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_129 |
|
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE0_INTR_IN_128 |
|
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE1_INTR_IN_128 |
|
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE0_INTR_IN_128 |
|
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE1_INTR_IN_128 |
|
MAIN_CTRL_MMR0_ACCESS_ERR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_128 |
| OUT Interrupt | Connected To |
|---|---|
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_32 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_32 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_32 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_33 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_33 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_33 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
C7X256V0_CLEC_GIC_SPI_IN_34 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
C7X256V1_CLEC_GIC_SPI_IN_34 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
WKUP_R5FSS0_CORE0_INTR_IN_34 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
C7X256V0_CLEC_GIC_SPI_IN_35 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
C7X256V1_CLEC_GIC_SPI_IN_35 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
WKUP_R5FSS0_CORE0_INTR_IN_35 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_4 |
C7X256V0_CLEC_GIC_SPI_IN_36 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_4 |
C7X256V1_CLEC_GIC_SPI_IN_36 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_4 |
WKUP_R5FSS0_CORE0_INTR_IN_36 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_5 |
C7X256V0_CLEC_GIC_SPI_IN_37 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_5 |
C7X256V1_CLEC_GIC_SPI_IN_37 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_5 |
WKUP_R5FSS0_CORE0_INTR_IN_37 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_6 |
C7X256V0_CLEC_GIC_SPI_IN_38 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_6 |
C7X256V1_CLEC_GIC_SPI_IN_38 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_6 |
WKUP_R5FSS0_CORE0_INTR_IN_38 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_7 |
C7X256V0_CLEC_GIC_SPI_IN_39 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_7 |
C7X256V1_CLEC_GIC_SPI_IN_39 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_7 |
WKUP_R5FSS0_CORE0_INTR_IN_39 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
C7X256V0_CLEC_GIC_SPI_IN_40 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
C7X256V1_CLEC_GIC_SPI_IN_40 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
WKUP_R5FSS0_CORE0_INTR_IN_40 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
C7X256V0_CLEC_GIC_SPI_IN_41 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
C7X256V1_CLEC_GIC_SPI_IN_41 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
WKUP_R5FSS0_CORE0_INTR_IN_41 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
C7X256V0_CLEC_GIC_SPI_IN_42 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
C7X256V1_CLEC_GIC_SPI_IN_42 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
WKUP_R5FSS0_CORE0_INTR_IN_42 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
C7X256V0_CLEC_GIC_SPI_IN_43 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
C7X256V1_CLEC_GIC_SPI_IN_43 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
WKUP_R5FSS0_CORE0_INTR_IN_43 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_12 |
C7X256V0_CLEC_GIC_SPI_IN_44 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_12 |
C7X256V1_CLEC_GIC_SPI_IN_44 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_12 |
WKUP_R5FSS0_CORE0_INTR_IN_44 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_13 |
C7X256V0_CLEC_GIC_SPI_IN_45 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_13 |
C7X256V1_CLEC_GIC_SPI_IN_45 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_13 |
WKUP_R5FSS0_CORE0_INTR_IN_45 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_14 |
C7X256V0_CLEC_GIC_SPI_IN_46 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_14 |
C7X256V1_CLEC_GIC_SPI_IN_46 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_14 |
WKUP_R5FSS0_CORE0_INTR_IN_46 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_15 |
C7X256V0_CLEC_GIC_SPI_IN_47 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_15 |
C7X256V1_CLEC_GIC_SPI_IN_47 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_15 |
WKUP_R5FSS0_CORE0_INTR_IN_47 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_16 |
R5FSS0_CORE0_INTR_IN_32 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_16 |
R5FSS0_CORE1_INTR_IN_32 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_17 |
R5FSS0_CORE0_INTR_IN_33 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_17 |
R5FSS0_CORE1_INTR_IN_33 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_18 |
R5FSS0_CORE0_INTR_IN_34 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_18 |
R5FSS0_CORE1_INTR_IN_34 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_19 |
R5FSS0_CORE0_INTR_IN_35 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_19 |
R5FSS0_CORE1_INTR_IN_35 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_20 |
R5FSS0_CORE0_INTR_IN_36 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_20 |
R5FSS0_CORE1_INTR_IN_36 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_21 |
R5FSS0_CORE0_INTR_IN_37 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_21 |
R5FSS0_CORE1_INTR_IN_37 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_22 |
R5FSS0_CORE0_INTR_IN_38 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_22 |
R5FSS0_CORE1_INTR_IN_38 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_23 |
R5FSS0_CORE0_INTR_IN_39 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_23 |
R5FSS0_CORE1_INTR_IN_39 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_24 |
R5FSS0_CORE0_INTR_IN_40 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_24 |
R5FSS0_CORE1_INTR_IN_40 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_25 |
R5FSS0_CORE0_INTR_IN_41 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_25 |
R5FSS0_CORE1_INTR_IN_41 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_26 |
R5FSS0_CORE0_INTR_IN_42 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_26 |
R5FSS0_CORE1_INTR_IN_42 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_27 |
R5FSS0_CORE0_INTR_IN_43 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_27 |
R5FSS0_CORE1_INTR_IN_43 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_28 |
R5FSS0_CORE0_INTR_IN_44 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_28 |
R5FSS0_CORE1_INTR_IN_44 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_29 |
R5FSS0_CORE0_INTR_IN_45 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_29 |
R5FSS0_CORE1_INTR_IN_45 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_30 |
R5FSS0_CORE0_INTR_IN_46 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_30 |
R5FSS0_CORE1_INTR_IN_46 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_31 |
R5FSS0_CORE0_INTR_IN_47 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_31 |
R5FSS0_CORE1_INTR_IN_47 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_32 |
R5FSS1_CORE0_INTR_IN_32 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_32 |
R5FSS1_CORE1_INTR_IN_32 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_33 |
R5FSS1_CORE0_INTR_IN_33 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_33 |
R5FSS1_CORE1_INTR_IN_33 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_34 |
R5FSS1_CORE0_INTR_IN_34 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_34 |
R5FSS1_CORE1_INTR_IN_34 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_35 |
R5FSS1_CORE0_INTR_IN_35 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_35 |
R5FSS1_CORE1_INTR_IN_35 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_36 |
R5FSS1_CORE0_INTR_IN_36 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_36 |
R5FSS1_CORE1_INTR_IN_36 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_37 |
R5FSS1_CORE0_INTR_IN_37 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_37 |
R5FSS1_CORE1_INTR_IN_37 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_38 |
R5FSS1_CORE0_INTR_IN_38 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_38 |
R5FSS1_CORE1_INTR_IN_38 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_39 |
R5FSS1_CORE0_INTR_IN_39 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_39 |
R5FSS1_CORE1_INTR_IN_39 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_40 |
R5FSS1_CORE0_INTR_IN_40 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_40 |
R5FSS1_CORE1_INTR_IN_40 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_41 |
R5FSS1_CORE0_INTR_IN_41 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_41 |
R5FSS1_CORE1_INTR_IN_41 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_42 |
R5FSS1_CORE0_INTR_IN_42 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_42 |
R5FSS1_CORE1_INTR_IN_42 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_43 |
R5FSS1_CORE0_INTR_IN_43 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_43 |
R5FSS1_CORE1_INTR_IN_43 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_44 |
R5FSS1_CORE0_INTR_IN_44 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_44 |
R5FSS1_CORE1_INTR_IN_44 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_45 |
R5FSS1_CORE0_INTR_IN_45 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_45 |
R5FSS1_CORE1_INTR_IN_45 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_46 |
R5FSS1_CORE0_INTR_IN_46 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_46 |
R5FSS1_CORE1_INTR_IN_46 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_47 |
R5FSS1_CORE0_INTR_IN_47 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_47 |
R5FSS1_CORE1_INTR_IN_47 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_48 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_16 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_49 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_17 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_50 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_18 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_51 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_19 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_52 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_20 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_53 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_21 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_54 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_22 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_55 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_23 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_56 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_24 |
|
MAIN_GPIOMUX_INTROUTER0_OUTP_OUT_57 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_25 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
PADCFG_CTRL0 |
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_129 |
|
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_129 |
|
|
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE0_INTR_IN_128 |
|
|
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE1_INTR_IN_128 |
|
|
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE0_INTR_IN_128 |
|
|
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE1_INTR_IN_128 |
|
|
PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_128 |
|
|
MCU_PADCFG_CTRL0 |
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_129 |
|
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_129 |
|
|
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE0_INTR_IN_128 |
|
|
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE1_INTR_IN_128 |
|
|
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE0_INTR_IN_128 |
|
|
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE1_INTR_IN_128 |
|
|
MCU_PADCFG_CTRL0_ACCESS_ERR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_128 |
| OUT Interrupt | Connected To |
|---|---|
|
MAIN_PSC0_PSC_ALLINT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_203 |
|
MAIN_PSC0_PSC_ALLINT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_203 |
|
MAIN_PSC0_PSC_ALLINT_OUT_0 |
R5FSS0_CORE0_INTR_IN_146 |
|
MAIN_PSC0_PSC_ALLINT_OUT_0 |
R5FSS0_CORE1_INTR_IN_146 |
|
MAIN_PSC0_PSC_ALLINT_OUT_0 |
R5FSS1_CORE0_INTR_IN_146 |
|
MAIN_PSC0_PSC_ALLINT_OUT_0 |
R5FSS1_CORE1_INTR_IN_146 |
|
MAIN_PSC0_PSC_ALLINT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_146 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
MCU_MCU_16FF0 |
MCU_MCU_16FF0_VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_101 |
|
MCU_MCU_16FF0_VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_102 |
|
|
MCU_CTRL_MMR0 |
MCU_CTRL_MMR0_IPC_SET0_IPC_SET_IPCFG_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_0 |
|
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_129 |
|
|
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_129 |
|
|
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE0_INTR_IN_128 |
|
|
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE1_INTR_IN_128 |
|
|
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE0_INTR_IN_128 |
|
|
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE1_INTR_IN_128 |
|
|
MCU_CTRL_MMR0_ACCESS_ERR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_128 |
| OUT Interrupt | Connected To |
|---|---|
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_104 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_104 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_104 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_105 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_105 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_105 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
C7X256V0_CLEC_GIC_SPI_IN_106 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
C7X256V1_CLEC_GIC_SPI_IN_106 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_2 |
WKUP_R5FSS0_CORE0_INTR_IN_106 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
C7X256V0_CLEC_GIC_SPI_IN_107 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
C7X256V1_CLEC_GIC_SPI_IN_107 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_3 |
WKUP_R5FSS0_CORE0_INTR_IN_107 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_88 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_88 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_8 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_88 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_89 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_89 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_9 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_89 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_90 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_90 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_10 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_90 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_91 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_91 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_11 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_91 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_12 |
WKUP_R5FSS0_CORE0_INTR_IN_50 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_13 |
WKUP_R5FSS0_CORE0_INTR_IN_51 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_14 |
WKUP_R5FSS0_CORE0_INTR_IN_52 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_15 |
WKUP_R5FSS0_CORE0_INTR_IN_53 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_16 |
R5FSS0_CORE0_INTR_IN_100 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_16 |
R5FSS0_CORE1_INTR_IN_100 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_17 |
R5FSS0_CORE0_INTR_IN_101 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_17 |
R5FSS0_CORE1_INTR_IN_101 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_18 |
R5FSS0_CORE0_INTR_IN_102 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_18 |
R5FSS0_CORE1_INTR_IN_102 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_19 |
R5FSS0_CORE0_INTR_IN_103 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_19 |
R5FSS0_CORE1_INTR_IN_103 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_20 |
R5FSS0_CORE0_INTR_IN_104 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_20 |
R5FSS0_CORE1_INTR_IN_104 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_21 |
R5FSS0_CORE0_INTR_IN_105 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_21 |
R5FSS0_CORE1_INTR_IN_105 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_22 |
R5FSS0_CORE0_INTR_IN_106 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_22 |
R5FSS0_CORE1_INTR_IN_106 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_23 |
R5FSS0_CORE0_INTR_IN_107 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_23 |
R5FSS0_CORE1_INTR_IN_107 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_24 |
R5FSS1_CORE0_INTR_IN_100 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_24 |
R5FSS1_CORE1_INTR_IN_100 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_25 |
R5FSS1_CORE0_INTR_IN_101 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_25 |
R5FSS1_CORE1_INTR_IN_101 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_26 |
R5FSS1_CORE0_INTR_IN_102 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_26 |
R5FSS1_CORE1_INTR_IN_102 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_27 |
R5FSS1_CORE0_INTR_IN_103 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_27 |
R5FSS1_CORE1_INTR_IN_103 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_28 |
R5FSS1_CORE0_INTR_IN_104 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_28 |
R5FSS1_CORE1_INTR_IN_104 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_29 |
R5FSS1_CORE0_INTR_IN_105 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_29 |
R5FSS1_CORE1_INTR_IN_105 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_30 |
R5FSS1_CORE0_INTR_IN_106 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_30 |
R5FSS1_CORE1_INTR_IN_106 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_31 |
R5FSS1_CORE0_INTR_IN_107 |
|
MCU_MCU_GPIOMUX_INTROUTER0_OUTP_OUT_31 |
R5FSS1_CORE1_INTR_IN_107 |
| OUT Interrupt | Connected To |
|---|---|
|
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_129 |
|
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_129 |
|
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE0_INTR_IN_128 |
|
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS0_CORE1_INTR_IN_128 |
|
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE0_INTR_IN_128 |
|
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
R5FSS1_CORE1_INTR_IN_128 |
|
WKUP_CTRL_MMR0_ACCESS_ERR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_128 |
| OUT Interrupt | Connected To |
|---|---|
|
CPSW0_CPTS_COMP_OUT_0 |
PINFUNCTION_CP_GEMAC_CPTS0_TS_COMPOUT_CP_GEMAC_CPTS0_TS_COMP_IN_0 |
|
CPSW0_CPTS_COMP_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_48 |
|
CPSW0_CPTS_COMP_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_48 |
|
CPSW0_CPTS_COMP_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_0 |
|
CPSW0_CPTS_COMP_OUT_0 |
R5FSS0_CORE0_INTR_IN_48 |
|
CPSW0_CPTS_COMP_OUT_0 |
R5FSS0_CORE1_INTR_IN_48 |
|
CPSW0_CPTS_COMP_OUT_0 |
R5FSS1_CORE0_INTR_IN_48 |
|
CPSW0_CPTS_COMP_OUT_0 |
R5FSS1_CORE1_INTR_IN_48 |
|
CPSW0_CPTS_COMP_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_48 |
|
CPSW0_CPTS_GENF0_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_16 |
|
CPSW0_CPTS_GENF1_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_17 |
|
CPSW0_CPTS_SYNC_OUT_0 |
PINFUNCTION_CP_GEMAC_CPTS0_TS_SYNCOUT_CP_GEMAC_CPTS0_TS_SYNC_IN_0 |
|
CPSW0_CPTS_SYNC_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_18 |
|
CPSW0_ECC_DED_PEND_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_67 |
|
CPSW0_ECC_SEC_PEND_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_3 |
|
CPSW0_EVNT_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_134 |
|
CPSW0_EVNT_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_134 |
|
CPSW0_EVNT_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_134 |
|
CPSW0_EVNT_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_134 |
|
CPSW0_EVNT_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_134 |
|
CPSW0_EVNT_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_134 |
|
CPSW0_EVNT_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_134 |
|
CPSW0_MDIO_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_135 |
|
CPSW0_MDIO_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_135 |
|
CPSW0_MDIO_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_135 |
|
CPSW0_MDIO_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_135 |
|
CPSW0_MDIO_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_135 |
|
CPSW0_MDIO_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_135 |
|
CPSW0_MDIO_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_135 |
|
CPSW0_STAT_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_136 |
|
CPSW0_STAT_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_136 |
|
CPSW0_STAT_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_136 |
|
CPSW0_STAT_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_136 |
|
CPSW0_STAT_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_136 |
|
CPSW0_STAT_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_136 |
|
CPSW0_STAT_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_136 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
DCC0 |
DCC0_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC0_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC0_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC0_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC0_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC0_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC0_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC0_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_112 |
|
|
DCC1 |
DCC1_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC1_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC1_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC1_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC1_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC1_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC1_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC1_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_113 |
|
|
DCC2 |
DCC2_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC2_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC2_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC2_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC2_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC2_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC2_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC2_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_114 |
|
|
DCC3 |
DCC3_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC3_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC3_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC3_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC3_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC3_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC3_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC3_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_115 |
|
|
DCC4 |
DCC4_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC4_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC4_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC4_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC4_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC4_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC4_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC4_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_116 |
|
|
DCC5 |
DCC5_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC5_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC5_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC5_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC5_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC5_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC5_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC5_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_117 |
|
|
DCC6 |
DCC6_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC6_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC6_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC6_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC6_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC6_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC6_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC6_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_79 |
|
|
DCC7 |
DCC7_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC7_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC7_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC7_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC7_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC7_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC7_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC7_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_73 |
|
|
DCC8 |
DCC8_INTR_DONE_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_128 |
|
DCC8_INTR_DONE_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_128 |
|
|
DCC8_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC8_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_109 |
|
|
DCC8_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_109 |
|
|
DCC8_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_109 |
|
|
DCC8_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_109 |
|
|
DCC8_INTR_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_223 |
|
|
MCU_DCC0 |
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_108 |
|
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_108 |
|
|
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_108 |
|
|
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_108 |
|
|
MCU_DCC0_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_108 |
|
|
MCU_DCC0_INTR_ERR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_37 |
|
|
MCU_DCC1 |
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_137 |
|
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_137 |
|
|
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_137 |
|
|
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_137 |
|
|
MCU_DCC1_INTR_DONE_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_137 |
|
|
MCU_DCC1_INTR_ERR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_36 |
| OUT Interrupt | Connected To |
|---|---|
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_64 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_64 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_1 |
R5FSS1_CORE0_INTR_IN_65 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_1 |
R5FSS1_CORE1_INTR_IN_65 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_2 |
R5FSS1_CORE0_INTR_IN_66 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_2 |
R5FSS1_CORE1_INTR_IN_66 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_3 |
R5FSS1_CORE0_INTR_IN_67 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_3 |
R5FSS1_CORE1_INTR_IN_67 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_4 |
R5FSS1_CORE0_INTR_IN_68 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_4 |
R5FSS1_CORE1_INTR_IN_68 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_5 |
R5FSS1_CORE0_INTR_IN_69 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_5 |
R5FSS1_CORE1_INTR_IN_69 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_6 |
R5FSS1_CORE0_INTR_IN_70 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_6 |
R5FSS1_CORE1_INTR_IN_70 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_7 |
R5FSS1_CORE0_INTR_IN_71 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_7 |
R5FSS1_CORE1_INTR_IN_71 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_8 |
R5FSS1_CORE0_INTR_IN_72 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_8 |
R5FSS1_CORE1_INTR_IN_72 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_9 |
R5FSS1_CORE0_INTR_IN_73 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_9 |
R5FSS1_CORE1_INTR_IN_73 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_10 |
R5FSS1_CORE0_INTR_IN_74 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_10 |
R5FSS1_CORE1_INTR_IN_74 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_11 |
R5FSS1_CORE0_INTR_IN_75 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_11 |
R5FSS1_CORE1_INTR_IN_75 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_12 |
R5FSS1_CORE0_INTR_IN_76 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_12 |
R5FSS1_CORE1_INTR_IN_76 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_13 |
R5FSS1_CORE0_INTR_IN_77 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_13 |
R5FSS1_CORE1_INTR_IN_77 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_14 |
R5FSS1_CORE0_INTR_IN_78 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_14 |
R5FSS1_CORE1_INTR_IN_78 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_15 |
R5FSS1_CORE0_INTR_IN_79 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_15 |
R5FSS1_CORE1_INTR_IN_79 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_16 |
R5FSS1_CORE0_INTR_IN_8 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_16 |
R5FSS1_CORE1_INTR_IN_8 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_17 |
R5FSS1_CORE0_INTR_IN_9 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_17 |
R5FSS1_CORE1_INTR_IN_9 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_18 |
R5FSS1_CORE0_INTR_IN_10 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_18 |
R5FSS1_CORE1_INTR_IN_10 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_19 |
R5FSS1_CORE0_INTR_IN_11 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_19 |
R5FSS1_CORE1_INTR_IN_11 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_20 |
R5FSS1_CORE0_INTR_IN_12 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_20 |
R5FSS1_CORE1_INTR_IN_12 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_21 |
R5FSS1_CORE0_INTR_IN_13 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_21 |
R5FSS1_CORE1_INTR_IN_13 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_22 |
R5FSS1_CORE0_INTR_IN_14 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_22 |
R5FSS1_CORE1_INTR_IN_14 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_23 |
R5FSS1_CORE0_INTR_IN_15 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_23 |
R5FSS1_CORE1_INTR_IN_15 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_24 |
R5FSS1_CORE0_INTR_IN_153 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_24 |
R5FSS1_CORE1_INTR_IN_153 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_25 |
R5FSS1_CORE0_INTR_IN_154 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_25 |
R5FSS1_CORE1_INTR_IN_154 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_26 |
R5FSS1_CORE0_INTR_IN_155 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_26 |
R5FSS1_CORE1_INTR_IN_155 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_27 |
R5FSS1_CORE0_INTR_IN_156 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_27 |
R5FSS1_CORE1_INTR_IN_156 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_28 |
R5FSS1_CORE0_INTR_IN_157 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_28 |
R5FSS1_CORE1_INTR_IN_157 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_29 |
R5FSS1_CORE0_INTR_IN_158 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_29 |
R5FSS1_CORE1_INTR_IN_158 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_30 |
R5FSS1_CORE0_INTR_IN_159 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_30 |
R5FSS1_CORE1_INTR_IN_159 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_31 |
R5FSS1_CORE0_INTR_IN_160 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_31 |
R5FSS1_CORE1_INTR_IN_160 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_32 |
C7X256V0_CLEC_GIC_SPI_IN_96 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_32 |
C7X256V1_CLEC_GIC_SPI_IN_96 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_33 |
C7X256V0_CLEC_GIC_SPI_IN_97 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_33 |
C7X256V1_CLEC_GIC_SPI_IN_97 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_34 |
C7X256V0_CLEC_GIC_SPI_IN_98 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_34 |
C7X256V1_CLEC_GIC_SPI_IN_98 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_35 |
C7X256V0_CLEC_GIC_SPI_IN_99 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_35 |
C7X256V1_CLEC_GIC_SPI_IN_99 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_36 |
C7X256V0_CLEC_GIC_SPI_IN_100 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_36 |
C7X256V1_CLEC_GIC_SPI_IN_100 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_37 |
C7X256V0_CLEC_GIC_SPI_IN_101 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_37 |
C7X256V1_CLEC_GIC_SPI_IN_101 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_38 |
C7X256V0_CLEC_GIC_SPI_IN_102 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_38 |
C7X256V1_CLEC_GIC_SPI_IN_102 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_39 |
C7X256V0_CLEC_GIC_SPI_IN_103 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_39 |
C7X256V1_CLEC_GIC_SPI_IN_103 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_40 |
WKUP_R5FSS0_CORE0_INTR_IN_64 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_41 |
WKUP_R5FSS0_CORE0_INTR_IN_65 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_42 |
WKUP_R5FSS0_CORE0_INTR_IN_66 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_43 |
WKUP_R5FSS0_CORE0_INTR_IN_67 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_44 |
WKUP_R5FSS0_CORE0_INTR_IN_68 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_45 |
WKUP_R5FSS0_CORE0_INTR_IN_69 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_46 |
WKUP_R5FSS0_CORE0_INTR_IN_70 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_47 |
WKUP_R5FSS0_CORE0_INTR_IN_71 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_48 |
WKUP_R5FSS0_CORE0_INTR_IN_72 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_49 |
WKUP_R5FSS0_CORE0_INTR_IN_73 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_50 |
WKUP_R5FSS0_CORE0_INTR_IN_74 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_51 |
WKUP_R5FSS0_CORE0_INTR_IN_75 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_52 |
WKUP_R5FSS0_CORE0_INTR_IN_76 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_53 |
WKUP_R5FSS0_CORE0_INTR_IN_77 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_54 |
WKUP_R5FSS0_CORE0_INTR_IN_78 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_55 |
WKUP_R5FSS0_CORE0_INTR_IN_79 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_56 |
WKUP_R5FSS0_CORE0_INTR_IN_80 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_57 |
WKUP_R5FSS0_CORE0_INTR_IN_81 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_58 |
WKUP_R5FSS0_CORE0_INTR_IN_82 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_59 |
WKUP_R5FSS0_CORE0_INTR_IN_83 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_60 |
WKUP_R5FSS0_CORE0_INTR_IN_84 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_61 |
WKUP_R5FSS0_CORE0_INTR_IN_85 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_62 |
WKUP_R5FSS0_CORE0_INTR_IN_86 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_63 |
WKUP_R5FSS0_CORE0_INTR_IN_87 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_64 |
WKUP_R5FSS0_CORE0_INTR_IN_88 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_65 |
WKUP_R5FSS0_CORE0_INTR_IN_89 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_66 |
WKUP_R5FSS0_CORE0_INTR_IN_90 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_67 |
WKUP_R5FSS0_CORE0_INTR_IN_91 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_68 |
WKUP_R5FSS0_CORE0_INTR_IN_92 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_69 |
WKUP_R5FSS0_CORE0_INTR_IN_93 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_70 |
WKUP_R5FSS0_CORE0_INTR_IN_94 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_71 |
WKUP_R5FSS0_CORE0_INTR_IN_95 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_72 |
WKUP_R5FSS0_CORE0_INTR_IN_8 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_73 |
WKUP_R5FSS0_CORE0_INTR_IN_9 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_74 |
WKUP_R5FSS0_CORE0_INTR_IN_10 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_75 |
WKUP_R5FSS0_CORE0_INTR_IN_11 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_76 |
WKUP_R5FSS0_CORE0_INTR_IN_12 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_77 |
WKUP_R5FSS0_CORE0_INTR_IN_13 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_78 |
WKUP_R5FSS0_CORE0_INTR_IN_14 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_79 |
WKUP_R5FSS0_CORE0_INTR_IN_15 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_84 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_16 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_85 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_17 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_86 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_18 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_87 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_19 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_88 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_20 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_89 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_21 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_90 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_22 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_91 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_23 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_92 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_24 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_93 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_25 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_94 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_26 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_95 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_27 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_96 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_28 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_97 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_29 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_98 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_30 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_99 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_31 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_100 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_16 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_101 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_17 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_102 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_18 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_103 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_19 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_104 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_20 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_105 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_21 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_106 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_22 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_107 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_23 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_108 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_24 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_109 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_25 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_110 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_26 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_111 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_27 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_112 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_28 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_113 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_29 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_114 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_30 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_115 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_31 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_152 |
R5FSS0_CORE0_INTR_IN_64 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_152 |
R5FSS0_CORE1_INTR_IN_64 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_153 |
R5FSS0_CORE0_INTR_IN_65 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_153 |
R5FSS0_CORE1_INTR_IN_65 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_154 |
R5FSS0_CORE0_INTR_IN_66 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_154 |
R5FSS0_CORE1_INTR_IN_66 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_155 |
R5FSS0_CORE0_INTR_IN_67 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_155 |
R5FSS0_CORE1_INTR_IN_67 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_156 |
R5FSS0_CORE0_INTR_IN_68 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_156 |
R5FSS0_CORE1_INTR_IN_68 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_157 |
R5FSS0_CORE0_INTR_IN_69 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_157 |
R5FSS0_CORE1_INTR_IN_69 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_158 |
R5FSS0_CORE0_INTR_IN_70 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_158 |
R5FSS0_CORE1_INTR_IN_70 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_159 |
R5FSS0_CORE0_INTR_IN_71 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_159 |
R5FSS0_CORE1_INTR_IN_71 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_160 |
R5FSS0_CORE0_INTR_IN_72 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_160 |
R5FSS0_CORE1_INTR_IN_72 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_161 |
R5FSS0_CORE0_INTR_IN_73 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_161 |
R5FSS0_CORE1_INTR_IN_73 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_162 |
R5FSS0_CORE0_INTR_IN_74 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_162 |
R5FSS0_CORE1_INTR_IN_74 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_163 |
R5FSS0_CORE0_INTR_IN_75 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_163 |
R5FSS0_CORE1_INTR_IN_75 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_164 |
R5FSS0_CORE0_INTR_IN_76 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_164 |
R5FSS0_CORE1_INTR_IN_76 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_165 |
R5FSS0_CORE0_INTR_IN_77 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_165 |
R5FSS0_CORE1_INTR_IN_77 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_166 |
R5FSS0_CORE0_INTR_IN_78 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_166 |
R5FSS0_CORE1_INTR_IN_78 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_167 |
R5FSS0_CORE0_INTR_IN_79 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_167 |
R5FSS0_CORE1_INTR_IN_79 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_168 |
R5FSS0_CORE0_INTR_IN_8 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_168 |
R5FSS0_CORE1_INTR_IN_8 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_169 |
R5FSS0_CORE0_INTR_IN_9 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_169 |
R5FSS0_CORE1_INTR_IN_9 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_170 |
R5FSS0_CORE0_INTR_IN_10 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_170 |
R5FSS0_CORE1_INTR_IN_10 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_171 |
R5FSS0_CORE0_INTR_IN_11 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_171 |
R5FSS0_CORE1_INTR_IN_11 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_172 |
R5FSS0_CORE0_INTR_IN_12 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_172 |
R5FSS0_CORE1_INTR_IN_12 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_173 |
R5FSS0_CORE0_INTR_IN_13 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_173 |
R5FSS0_CORE1_INTR_IN_13 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_174 |
R5FSS0_CORE0_INTR_IN_14 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_174 |
R5FSS0_CORE1_INTR_IN_14 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_175 |
R5FSS0_CORE0_INTR_IN_15 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_175 |
R5FSS0_CORE1_INTR_IN_15 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_176 |
R5FSS0_CORE0_INTR_IN_153 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_176 |
R5FSS0_CORE1_INTR_IN_153 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_177 |
R5FSS0_CORE0_INTR_IN_154 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_177 |
R5FSS0_CORE1_INTR_IN_154 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_178 |
R5FSS0_CORE0_INTR_IN_155 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_178 |
R5FSS0_CORE1_INTR_IN_155 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_179 |
R5FSS0_CORE0_INTR_IN_156 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_179 |
R5FSS0_CORE1_INTR_IN_156 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_180 |
R5FSS0_CORE0_INTR_IN_157 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_180 |
R5FSS0_CORE1_INTR_IN_157 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_181 |
R5FSS0_CORE0_INTR_IN_158 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_181 |
R5FSS0_CORE1_INTR_IN_158 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_182 |
R5FSS0_CORE0_INTR_IN_159 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_182 |
R5FSS0_CORE1_INTR_IN_159 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_183 |
R5FSS0_CORE0_INTR_IN_160 |
|
DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_OUT_183 |
R5FSS0_CORE1_INTR_IN_160 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
TIMER0 |
TIMER0_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_152 |
|
TIMER0_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_152 |
|
|
TIMER0_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_24 |
|
|
TIMER0_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_24 |
|
|
TIMER0_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_24 |
|
|
TIMER0_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_24 |
|
|
TIMER0_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_216 |
|
|
TIMER0_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_0 |
|
|
TIMER1 |
TIMER1_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_153 |
|
TIMER1_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_153 |
|
|
TIMER1_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_25 |
|
|
TIMER1_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_25 |
|
|
TIMER1_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_25 |
|
|
TIMER1_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_25 |
|
|
TIMER1_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_217 |
|
|
TIMER1_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_1 |
|
|
TIMER10 |
TIMER10_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_66 |
|
TIMER10_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_66 |
|
|
TIMER10_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_266 |
|
|
TIMER10_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_266 |
|
|
TIMER10_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_266 |
|
|
TIMER10_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_266 |
|
|
TIMER10_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_226 |
|
|
TIMER11 |
TIMER11_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_67 |
|
TIMER11_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_67 |
|
|
TIMER11_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_267 |
|
|
TIMER11_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_267 |
|
|
TIMER11_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_267 |
|
|
TIMER11_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_267 |
|
|
TIMER11_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_227 |
|
|
TIMER12 |
TIMER12_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_68 |
|
TIMER12_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_68 |
|
|
TIMER12_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_268 |
|
|
TIMER12_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_268 |
|
|
TIMER12_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_268 |
|
|
TIMER12_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_268 |
|
|
TIMER12_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_228 |
|
|
TIMER13 |
TIMER13_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_69 |
|
TIMER13_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_69 |
|
|
TIMER13_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_269 |
|
|
TIMER13_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_269 |
|
|
TIMER13_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_269 |
|
|
TIMER13_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_269 |
|
|
TIMER13_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_229 |
|
|
TIMER14 |
TIMER14_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_70 |
|
TIMER14_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_70 |
|
|
TIMER14_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_270 |
|
|
TIMER14_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_270 |
|
|
TIMER14_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_270 |
|
|
TIMER14_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_270 |
|
|
TIMER14_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_230 |
|
|
TIMER15 |
TIMER15_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_71 |
|
TIMER15_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_71 |
|
|
TIMER15_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_271 |
|
|
TIMER15_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_271 |
|
|
TIMER15_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_271 |
|
|
TIMER15_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_271 |
|
|
TIMER15_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_231 |
|
|
TIMER2 |
TIMER2_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_154 |
|
TIMER2_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_154 |
|
|
TIMER2_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_26 |
|
|
TIMER2_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_26 |
|
|
TIMER2_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_26 |
|
|
TIMER2_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_26 |
|
|
TIMER2_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_218 |
|
|
TIMER2_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_2 |
|
|
TIMER3 |
TIMER3_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_155 |
|
TIMER3_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_155 |
|
|
TIMER3_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_27 |
|
|
TIMER3_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_27 |
|
|
TIMER3_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_27 |
|
|
TIMER3_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_27 |
|
|
TIMER3_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_219 |
|
|
TIMER3_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_3 |
|
|
TIMER4 |
TIMER4_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_156 |
|
TIMER4_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_156 |
|
|
TIMER4_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_28 |
|
|
TIMER4_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_28 |
|
|
TIMER4_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_28 |
|
|
TIMER4_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_28 |
|
|
TIMER4_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_220 |
|
|
TIMER4_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_4 |
|
|
TIMER5 |
TIMER5_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_157 |
|
TIMER5_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_157 |
|
|
TIMER5_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_29 |
|
|
TIMER5_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_29 |
|
|
TIMER5_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_29 |
|
|
TIMER5_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_29 |
|
|
TIMER5_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_221 |
|
|
TIMER5_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_5 |
|
|
TIMER6 |
TIMER6_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_158 |
|
TIMER6_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_158 |
|
|
TIMER6_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_22 |
|
|
TIMER6_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_22 |
|
|
TIMER6_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_22 |
|
|
TIMER6_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_22 |
|
|
TIMER6_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_222 |
|
|
TIMER6_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_6 |
|
|
TIMER7 |
TIMER7_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_159 |
|
TIMER7_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_159 |
|
|
TIMER7_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_23 |
|
|
TIMER7_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_23 |
|
|
TIMER7_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_23 |
|
|
TIMER7_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_23 |
|
|
TIMER7_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_223 |
|
|
TIMER7_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_7 |
|
|
TIMER8 |
TIMER8_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_64 |
|
TIMER8_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_64 |
|
|
TIMER8_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_264 |
|
|
TIMER8_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_264 |
|
|
TIMER8_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_264 |
|
|
TIMER8_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_264 |
|
|
TIMER8_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_224 |
|
|
TIMER8_TIMER_PWM_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_8 |
|
|
TIMER9 |
TIMER9_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_65 |
|
TIMER9_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_65 |
|
|
TIMER9_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_265 |
|
|
TIMER9_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_265 |
|
|
TIMER9_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_265 |
|
|
TIMER9_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_265 |
|
|
TIMER9_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_225 |
|
|
WKUP_TIMER0 |
WKUP_TIMER0_INTR_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_138 |
|
WKUP_TIMER0_TIMER_CLKSTOP_WAKEUP_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_28 |
|
|
WKUP_TIMER0_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_214 |
|
|
WKUP_TIMER1 |
WKUP_TIMER1_INTR_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_139 |
|
WKUP_TIMER1_TIMER_CLKSTOP_WAKEUP_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_29 |
|
|
WKUP_TIMER1_TIMER_PWM_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_215 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
ECAP0 |
ECAP0_ECAP_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_145 |
|
ECAP0_ECAP_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_145 |
|
|
ECAP0_ECAP_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_83 |
|
|
ECAP0_ECAP_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_83 |
|
|
ECAP0_ECAP_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_83 |
|
|
ECAP0_ECAP_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_83 |
|
|
ECAP1 |
ECAP1_ECAP_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_146 |
|
ECAP1_ECAP_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_146 |
|
|
ECAP1_ECAP_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_84 |
|
|
ECAP1_ECAP_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_84 |
|
|
ECAP1_ECAP_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_84 |
|
|
ECAP1_ECAP_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_84 |
|
|
ECAP2 |
ECAP2_ECAP_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_147 |
|
ECAP2_ECAP_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_147 |
|
|
ECAP2_ECAP_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_85 |
|
|
ECAP2_ECAP_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_85 |
|
|
ECAP2_ECAP_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_85 |
|
|
ECAP2_ECAP_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_85 |
|
|
ECAP3 |
ECAP3_ECAP_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_148 |
|
ECAP3_ECAP_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_148 |
|
|
ECAP3_ECAP_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_86 |
|
|
ECAP3_ECAP_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_86 |
|
|
ECAP3 |
ECAP3_ECAP_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_86 |
|
ECAP3_ECAP_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_86 |
|
|
ECAP4 |
ECAP4_ECAP_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_149 |
|
ECAP4_ECAP_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_149 |
|
|
ECAP4_ECAP_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_87 |
|
|
ECAP4_ECAP_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_87 |
|
|
ECAP4_ECAP_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_87 |
|
|
ECAP4_ECAP_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_87 |
|
|
ECAP5 |
ECAP5_ECAP_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_150 |
|
ECAP5_ECAP_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_150 |
|
|
ECAP5_ECAP_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_88 |
|
|
ECAP5_ECAP_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_88 |
|
|
ECAP5_ECAP_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_88 |
|
|
ECAP5_ECAP_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_88 |
| OUT Interrupt | Connected To |
|---|---|
|
MMCSD0_EMMCSDSS_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_165 |
|
MMCSD0_EMMCSDSS_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_165 |
|
MMCSD0_EMMCSDSS_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_161 |
|
MMCSD0_EMMCSDSS_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_161 |
|
MMCSD0_EMMCSDSS_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_161 |
|
MMCSD0_EMMCSDSS_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_161 |
|
MMCSD0_EMMCSDSS_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_161 |
|
MMCSD0_EMMCSDSS_RXMEM_CORR_ERR_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_54 |
|
MMCSD0_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_55 |
|
MMCSD0_EMMCSDSS_TXMEM_CORR_ERR_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_56 |
|
MMCSD0_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_57 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
WKUP_ESM0 |
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_37 |
|
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_140 |
|
|
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_140 |
|
|
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_140 |
|
|
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_140 |
|
|
WKUP_ESM0_ESM_INT_CFG_LVL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_140 |
|
|
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_38 |
|
|
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_141 |
|
|
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_141 |
|
|
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_141 |
|
|
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_141 |
|
|
WKUP_ESM0_ESM_INT_HI_LVL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_141 |
|
|
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_39 |
|
|
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_142 |
|
|
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_142 |
|
|
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_142 |
|
|
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_142 |
|
|
WKUP_ESM0_ESM_INT_LOW_LVL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_142 |
|
|
ESM0 |
ESM0_ESM_INT_CFG_LVL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_180 |
|
ESM0_ESM_INT_CFG_LVL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_180 |
|
|
ESM0_ESM_INT_CFG_LVL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_0 |
|
|
ESM0_ESM_INT_CFG_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_167 |
|
|
ESM0_ESM_INT_CFG_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_167 |
|
|
ESM0_ESM_INT_CFG_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_167 |
|
|
ESM0_ESM_INT_CFG_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_167 |
|
|
ESM0_ESM_INT_CFG_LVL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_167 |
|
|
ESM0_ESM_INT_HI_LVL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_181 |
|
|
ESM0_ESM_INT_HI_LVL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_181 |
|
|
ESM0_ESM_INT_HI_LVL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_1 |
|
|
ESM0_ESM_INT_HI_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_168 |
|
|
ESM0_ESM_INT_HI_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_168 |
|
|
ESM0_ESM_INT_HI_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_168 |
|
|
ESM0_ESM_INT_HI_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_168 |
|
|
ESM0_ESM_INT_HI_LVL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_168 |
|
|
ESM0_ESM_INT_LOW_LVL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_182 |
|
|
ESM0_ESM_INT_LOW_LVL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_182 |
|
|
ESM0_ESM_INT_LOW_LVL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_2 |
|
|
ESM0_ESM_INT_LOW_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_169 |
|
|
ESM0_ESM_INT_LOW_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_169 |
|
|
ESM0_ESM_INT_LOW_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_169 |
|
|
ESM0_ESM_INT_LOW_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_169 |
|
|
ESM0_ESM_INT_LOW_LVL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_169 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
FSS1_FSAS_0 |
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_169 |
|
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_169 |
|
|
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_142 |
|
|
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_181 |
|
|
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_181 |
|
|
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_181 |
|
|
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_181 |
|
|
FSS1_FSAS_0_ECC_INTR_ERR_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_181 |
|
|
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_175 |
|
|
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_175 |
|
|
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_180 |
|
|
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_180 |
|
|
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_180 |
|
|
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_180 |
|
|
FSS1_FSAS_0_OTFA_INTR_ERR_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_180 |
|
|
FSS1_HYPERBUS1P0_0 |
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_179 |
|
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_179 |
|
|
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_179 |
|
|
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_179 |
|
|
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_179 |
|
|
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_179 |
|
|
FSS1_HYPERBUS1P0_0_HPB_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_179 |
|
|
FSS1_HYPERBUS_ECC_AGGR_0 |
FSS1_HYPERBUS_ECC_AGGR_0_HPB_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_143 |
|
FSS1_HYPERBUS_ECC_AGGR_0_HPB_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_144 |
|
|
FSS1_MISC_0 |
FSS1_MISC_0_ECC_INTR_ERR_PEND_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_147 |
|
FSS1_OSPI_0 |
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_178 |
|
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_178 |
|
|
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_178 |
|
|
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_178 |
|
|
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_178 |
|
|
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_178 |
|
|
FSS1_OSPI_0_OSPI_LVL_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_178 |
|
|
FSS1_OSPI_ECC_AGGR_0 |
FSS1_OSPI_ECC_AGGR_0_OSPI_ECC_CORR_LVL_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_12 |
|
FSS1_OSPI_ECC_AGGR_0_OSPI_ECC_UNCORR_LVL_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_75 |
|
|
FSS0 |
FSS0_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_145 |
|
FSS0_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_146 |
|
|
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_170 |
|
|
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_170 |
|
|
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_141 |
|
|
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_182 |
|
|
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_182 |
|
|
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_182 |
|
|
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_182 |
|
|
FSS0_FSAS_ECC_INTR_ERR_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_182 |
|
|
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_173 |
|
|
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_173 |
|
|
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_173 |
|
|
FSS0 |
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_173 |
|
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_173 |
|
|
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_173 |
|
|
FSS0_FSAS_FOTA_STAT_ERR_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_173 |
|
|
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_172 |
|
|
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_172 |
|
|
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_172 |
|
|
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_172 |
|
|
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_172 |
|
|
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_172 |
|
|
FSS0_FSAS_FOTA_STAT_INTR_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_172 |
|
|
FSS0_OSPI0_ECC_CORR_LVL_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_11 |
|
|
FSS0_OSPI0_ECC_UNCORR_LVL_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_74 |
|
|
FSS0_OSPI0_LVL_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_171 |
|
|
FSS0_OSPI0_LVL_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_171 |
|
|
FSS0_OSPI0_LVL_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_171 |
|
|
FSS0_OSPI0_LVL_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_171 |
|
|
FSS0_OSPI0_LVL_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_171 |
|
|
FSS0_OSPI0_LVL_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_171 |
|
|
FSS0_OSPI0_LVL_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_171 |
|
|
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_174 |
|
|
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_174 |
|
|
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_174 |
|
|
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_174 |
|
|
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_174 |
|
|
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_174 |
|
|
FSS0_OTFA_INTR_ERR_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_174 |
| OUT Interrupt | Connected To |
|---|---|
|
GPIO0_GPIO_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_0 |
|
GPIO0_GPIO_OUT_1 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_1 |
|
GPIO0_GPIO_OUT_2 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_2 |
|
GPIO0_GPIO_OUT_3 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_3 |
|
GPIO0_GPIO_OUT_4 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_4 |
|
GPIO0_GPIO_OUT_5 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_5 |
|
GPIO0_GPIO_OUT_6 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_6 |
|
GPIO0_GPIO_OUT_7 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_7 |
|
GPIO0_GPIO_OUT_8 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_8 |
|
GPIO0_GPIO_OUT_9 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_9 |
|
GPIO0_GPIO_OUT_10 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_10 |
|
GPIO0_GPIO_OUT_11 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_11 |
|
GPIO0_GPIO_OUT_12 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_12 |
|
GPIO0_GPIO_OUT_13 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_13 |
|
GPIO0_GPIO_OUT_14 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_14 |
|
GPIO0_GPIO_OUT_15 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_15 |
|
GPIO0_GPIO_OUT_16 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_16 |
|
GPIO0_GPIO_OUT_17 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_17 |
|
GPIO0_GPIO_OUT_18 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_18 |
|
GPIO0_GPIO_OUT_19 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_19 |
|
GPIO0_GPIO_OUT_20 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_20 |
|
GPIO0_GPIO_OUT_21 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_21 |
|
GPIO0_GPIO_OUT_22 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_22 |
|
GPIO0_GPIO_OUT_23 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_23 |
|
GPIO0_GPIO_OUT_24 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_24 |
|
GPIO0_GPIO_OUT_25 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_25 |
|
GPIO0_GPIO_OUT_26 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_26 |
|
GPIO0_GPIO_OUT_27 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_27 |
|
GPIO0_GPIO_OUT_28 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_28 |
|
GPIO0_GPIO_OUT_29 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_29 |
|
GPIO0_GPIO_OUT_30 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_30 |
|
GPIO0_GPIO_OUT_31 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_31 |
|
GPIO0_GPIO_OUT_32 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_32 |
|
GPIO0_GPIO_OUT_33 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_33 |
|
GPIO0_GPIO_OUT_34 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_34 |
|
GPIO0_GPIO_OUT_35 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_35 |
|
GPIO0_GPIO_OUT_36 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_36 |
|
GPIO0_GPIO_OUT_37 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_37 |
|
GPIO0_GPIO_OUT_38 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_38 |
|
GPIO0_GPIO_OUT_39 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_39 |
|
GPIO0_GPIO_OUT_40 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_40 |
|
GPIO0_GPIO_OUT_41 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_41 |
|
GPIO0_GPIO_OUT_42 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_42 |
|
GPIO0_GPIO_OUT_43 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_43 |
|
GPIO0_GPIO_OUT_44 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_44 |
|
GPIO0_GPIO_OUT_45 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_45 |
|
GPIO0_GPIO_OUT_46 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_46 |
|
GPIO0_GPIO_OUT_47 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_47 |
|
GPIO0_GPIO_OUT_48 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_48 |
|
GPIO0_GPIO_OUT_49 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_49 |
|
GPIO0_GPIO_OUT_50 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_50 |
|
GPIO0_GPIO_OUT_51 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_51 |
|
GPIO0_GPIO_OUT_52 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_52 |
|
GPIO0_GPIO_OUT_55 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_55 |
|
GPIO0_GPIO_OUT_56 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_56 |
|
GPIO0_GPIO_OUT_57 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_57 |
|
GPIO0_GPIO_OUT_58 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_58 |
|
GPIO0_GPIO_OUT_59 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_59 |
|
GPIO0_GPIO_OUT_62 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_62 |
|
GPIO0_GPIO_OUT_63 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_63 |
|
GPIO0_GPIO_OUT_64 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_64 |
|
GPIO0_GPIO_OUT_65 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_65 |
|
GPIO0_GPIO_OUT_66 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_66 |
|
GPIO0_GPIO_OUT_67 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_67 |
|
GPIO0_GPIO_OUT_68 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_68 |
|
GPIO0_GPIO_OUT_69 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_69 |
|
GPIO0_GPIO_OUT_70 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_70 |
|
GPIO0_GPIO_OUT_71 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_71 |
|
GPIO0_GPIO_OUT_72 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_72 |
|
GPIO0_GPIO_OUT_73 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_73 |
|
GPIO0_GPIO_OUT_74 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_74 |
|
GPIO0_GPIO_OUT_75 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_75 |
|
GPIO0_GPIO_OUT_76 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_76 |
|
GPIO0_GPIO_OUT_77 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_77 |
|
GPIO0_GPIO_OUT_78 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_78 |
|
GPIO0_GPIO_OUT_79 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_79 |
|
GPIO0_GPIO_OUT_80 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_80 |
|
GPIO0_GPIO_OUT_81 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_81 |
|
GPIO0_GPIO_OUT_82 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_82 |
|
GPIO0_GPIO_OUT_83 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_83 |
|
GPIO0_GPIO_OUT_84 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_84 |
|
GPIO0_GPIO_OUT_85 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_85 |
|
GPIO0_GPIO_OUT_86 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_86 |
|
GPIO0_GPIO_OUT_87 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_87 |
|
GPIO0_GPIO_OUT_88 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_88 |
|
GPIO0_GPIO_OUT_89 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_89 |
|
GPIO0_GPIO_OUT_90 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_90 |
|
GPIO0_GPIO_OUT_91 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_91 |
|
GPIO0_GPIO_OUT_92 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_92 |
|
GPIO0_GPIO_BANK_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_192 |
|
GPIO0_GPIO_BANK_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_56 |
|
GPIO0_GPIO_BANK_OUT_1 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_193 |
|
GPIO0_GPIO_BANK_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_57 |
|
GPIO0_GPIO_BANK_OUT_2 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_194 |
|
GPIO0_GPIO_BANK_OUT_3 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_195 |
|
GPIO0_GPIO_BANK_OUT_4 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_196 |
|
GPIO0_GPIO_BANK_OUT_5 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_197 |
|
GPIO1_GPIO_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_96 |
|
GPIO1_GPIO_OUT_1 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_97 |
|
GPIO1_GPIO_OUT_2 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_98 |
|
GPIO1_GPIO_OUT_3 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_99 |
|
GPIO1_GPIO_OUT_4 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_100 |
|
GPIO1_GPIO_OUT_5 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_101 |
|
GPIO1_GPIO_OUT_6 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_102 |
|
GPIO1_GPIO_OUT_7 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_103 |
|
GPIO1_GPIO_OUT_8 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_104 |
|
GPIO1_GPIO_OUT_9 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_105 |
|
GPIO1_GPIO_OUT_10 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_106 |
|
GPIO1_GPIO_OUT_11 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_107 |
|
GPIO1_GPIO_OUT_12 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_108 |
|
GPIO1_GPIO_OUT_13 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_109 |
|
GPIO1_GPIO_OUT_14 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_110 |
|
GPIO1_GPIO_OUT_15 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_111 |
|
GPIO1_GPIO_OUT_16 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_112 |
|
GPIO1_GPIO_OUT_17 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_113 |
|
GPIO1_GPIO_OUT_18 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_114 |
|
GPIO1_GPIO_OUT_19 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_115 |
|
GPIO1_GPIO_OUT_20 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_116 |
|
GPIO1_GPIO_OUT_21 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_117 |
|
GPIO1_GPIO_OUT_22 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_118 |
|
GPIO1_GPIO_OUT_23 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_119 |
|
GPIO1_GPIO_OUT_24 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_120 |
|
GPIO1_GPIO_OUT_25 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_121 |
|
GPIO1_GPIO_OUT_26 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_122 |
|
GPIO1_GPIO_OUT_27 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_123 |
|
GPIO1_GPIO_OUT_28 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_124 |
|
GPIO1_GPIO_OUT_29 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_125 |
|
GPIO1_GPIO_OUT_30 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_126 |
|
GPIO1_GPIO_OUT_31 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_127 |
|
GPIO1_GPIO_OUT_32 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_128 |
|
GPIO1_GPIO_OUT_33 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_129 |
|
GPIO1_GPIO_OUT_34 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_130 |
|
GPIO1_GPIO_OUT_35 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_131 |
|
GPIO1_GPIO_OUT_36 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_132 |
|
GPIO1_GPIO_OUT_37 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_133 |
|
GPIO1_GPIO_OUT_38 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_134 |
|
GPIO1_GPIO_OUT_39 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_135 |
|
GPIO1_GPIO_OUT_40 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_136 |
|
GPIO1_GPIO_OUT_41 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_137 |
|
GPIO1_GPIO_OUT_42 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_138 |
|
GPIO1_GPIO_OUT_43 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_139 |
|
GPIO1_GPIO_OUT_44 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_140 |
|
GPIO1_GPIO_OUT_45 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_141 |
|
GPIO1_GPIO_OUT_46 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_142 |
|
GPIO1_GPIO_OUT_47 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_143 |
|
GPIO1_GPIO_OUT_48 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_144 |
|
GPIO1_GPIO_OUT_49 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_145 |
|
GPIO1_GPIO_OUT_50 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_146 |
|
GPIO1_GPIO_OUT_72 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_168 |
|
GPIO1_GPIO_OUT_74 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_170 |
|
GPIO1_GPIO_OUT_75 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_171 |
|
GPIO1_GPIO_OUT_76 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_172 |
|
GPIO1_GPIO_OUT_77 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_173 |
|
GPIO1_GPIO_OUT_78 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_174 |
|
GPIO1_GPIO_OUT_79 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_175 |
|
GPIO1_GPIO_OUT_80 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_176 |
|
GPIO1_GPIO_OUT_81 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_177 |
|
GPIO1_GPIO_OUT_82 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_178 |
|
GPIO1_GPIO_OUT_83 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_179 |
|
GPIO1_GPIO_OUT_84 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_180 |
|
GPIO1_GPIO_OUT_85 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_181 |
|
GPIO1_GPIO_BANK_OUT_0 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_200 |
|
GPIO1_GPIO_BANK_OUT_1 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_201 |
|
GPIO1_GPIO_BANK_OUT_2 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_202 |
|
GPIO1_GPIO_BANK_OUT_3 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_203 |
|
GPIO1_GPIO_BANK_OUT_4 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_204 |
|
GPIO1_GPIO_BANK_OUT_5 |
MAIN_GPIOMUX_INTROUTER0_IN_IN_205 |
|
MCU_GPIO0_GPIO_OUT_0 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_0 |
|
MCU_GPIO0_GPIO_OUT_1 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_1 |
|
MCU_GPIO0_GPIO_OUT_2 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_2 |
|
MCU_GPIO0_GPIO_OUT_3 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_3 |
|
MCU_GPIO0_GPIO_OUT_4 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_4 |
|
MCU_GPIO0_GPIO_OUT_5 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_5 |
|
MCU_GPIO0_GPIO_OUT_6 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_6 |
|
MCU_GPIO0_GPIO_OUT_7 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_7 |
|
MCU_GPIO0_GPIO_OUT_8 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_8 |
|
MCU_GPIO0_GPIO_OUT_9 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_9 |
|
MCU_GPIO0_GPIO_OUT_10 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_10 |
|
MCU_GPIO0_GPIO_OUT_11 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_11 |
|
MCU_GPIO0_GPIO_OUT_12 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_12 |
|
MCU_GPIO0_GPIO_OUT_13 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_13 |
|
MCU_GPIO0_GPIO_OUT_14 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_14 |
|
MCU_GPIO0_GPIO_OUT_15 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_15 |
|
MCU_GPIO0_GPIO_OUT_16 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_16 |
|
MCU_GPIO0_GPIO_OUT_19 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_19 |
|
MCU_GPIO0_GPIO_OUT_20 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_20 |
|
MCU_GPIO0_GPIO_OUT_21 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_21 |
|
MCU_GPIO0_GPIO_OUT_22 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_22 |
|
MCU_GPIO0_GPIO_OUT_23 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_23 |
|
MCU_GPIO0_GPIO_OUT_24 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_24 |
|
MCU_GPIO0_GPIO_OUT_25 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_25 |
|
MCU_GPIO0_GPIO_BANK_OUT_0 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_30 |
|
MCU_GPIO0_GPIO_BANK_OUT_1 |
MCU_MCU_GPIOMUX_INTROUTER0_IN_IN_31 |
|
MCU_GPIO0_GPIO_LVL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_18 |
| OUT Interrupt | Connected To |
|---|---|
|
WKUP_GTC0_GTC_PUSH_EVENT_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_11 |
| OUT Interrupt | Connected To |
|---|---|
|
WKUP_ICEMELTER0_PSC_FORCE_POWER_ON_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_23 |
| OUT Interrupt | Connected To |
|---|---|
|
AASRC0_ERR_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_54 |
|
AASRC0_ERR_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_54 |
|
AASRC0_ERR_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_54 |
|
AASRC0_ERR_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_54 |
|
AASRC0_ERR_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_54 |
|
AASRC0_ERR_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_54 |
|
AASRC0_INFIFO_DMA_OUT_0 |
PDMA_AASRC0_6_INFIFO_EVT_IN_0 |
|
AASRC0_INFIFO_DMA_OUT_1 |
PDMA_AASRC0_6_INFIFO_EVT_IN_1 |
|
AASRC0_INFIFO_DMA_OUT_2 |
PDMA_AASRC0_6_INFIFO_EVT_IN_2 |
|
AASRC0_INFIFO_DMA_OUT_3 |
PDMA_AASRC0_6_INFIFO_EVT_IN_3 |
|
AASRC0_INFIFO_DMA_OUT_4 |
PDMA_AASRC0_6_INFIFO_EVT_IN_4 |
|
AASRC0_INFIFO_DMA_OUT_5 |
PDMA_AASRC0_6_INFIFO_EVT_IN_5 |
|
AASRC0_INFIFO_DMA_OUT_6 |
PDMA_AASRC0_6_INFIFO_EVT_IN_6 |
|
AASRC0_INFIFO_DMA_OUT_7 |
PDMA_AASRC0_6_INFIFO_EVT_IN_7 |
|
AASRC0_INFIFO_DMA_OUT_8 |
PDMA_AASRC0_6_INFIFO_EVT_IN_8 |
|
AASRC0_INFIFO_DMA_OUT_9 |
PDMA_AASRC0_6_INFIFO_EVT_IN_9 |
|
AASRC0_INFIFO_DMA_OUT_10 |
PDMA_AASRC0_6_INFIFO_EVT_IN_10 |
|
AASRC0_INFIFO_DMA_OUT_11 |
PDMA_AASRC0_6_INFIFO_EVT_IN_11 |
|
AASRC0_INFIFO_DMA_OUT_12 |
PDMA_AASRC0_6_INFIFO_EVT_IN_12 |
|
AASRC0_INFIFO_DMA_OUT_13 |
PDMA_AASRC0_6_INFIFO_EVT_IN_13 |
|
AASRC0_INFIFO_DMA_OUT_14 |
PDMA_AASRC0_6_INFIFO_EVT_IN_14 |
|
AASRC0_INFIFO_DMA_OUT_15 |
PDMA_AASRC0_6_INFIFO_EVT_IN_15 |
|
AASRC0_INFIFO_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_50 |
|
AASRC0_INFIFO_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_50 |
|
AASRC0_INFIFO_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_50 |
|
AASRC0_INFIFO_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_50 |
|
AASRC0_INFIFO_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_50 |
|
AASRC0_INFIFO_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_50 |
|
AASRC0_INGROUP_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_51 |
|
AASRC0_INGROUP_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_51 |
|
AASRC0_INGROUP_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_51 |
|
AASRC0_INGROUP_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_51 |
|
AASRC0_INGROUP_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_51 |
|
AASRC0_INGROUP_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_51 |
|
AASRC0_INGRP_DMA_OUT_0 |
PDMA_AASRC0_6_INGRP_EVT_IN_0 |
|
AASRC0_INGRP_DMA_OUT_1 |
PDMA_AASRC0_6_INGRP_EVT_IN_1 |
|
AASRC0_INGRP_DMA_OUT_2 |
PDMA_AASRC0_6_INGRP_EVT_IN_2 |
|
AASRC0_INGRP_DMA_OUT_3 |
PDMA_AASRC0_6_INGRP_EVT_IN_3 |
|
AASRC0_OUTFIFO_DMA_OUT_0 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_0 |
|
AASRC0_OUTFIFO_DMA_OUT_1 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_1 |
|
AASRC0_OUTFIFO_DMA_OUT_2 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_2 |
|
AASRC0_OUTFIFO_DMA_OUT_3 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_3 |
|
AASRC0_OUTFIFO_DMA_OUT_4 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_4 |
|
AASRC0_OUTFIFO_DMA_OUT_5 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_5 |
|
AASRC0_OUTFIFO_DMA_OUT_6 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_6 |
|
AASRC0_OUTFIFO_DMA_OUT_7 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_7 |
|
AASRC0_OUTFIFO_DMA_OUT_8 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_8 |
|
AASRC0_OUTFIFO_DMA_OUT_9 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_9 |
|
AASRC0_OUTFIFO_DMA_OUT_10 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_10 |
|
AASRC0_OUTFIFO_DMA_OUT_11 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_11 |
|
AASRC0_OUTFIFO_DMA_OUT_12 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_12 |
|
AASRC0_OUTFIFO_DMA_OUT_13 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_13 |
|
AASRC0_OUTFIFO_DMA_OUT_14 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_14 |
|
AASRC0_OUTFIFO_DMA_OUT_15 |
PDMA_AASRC0_6_OUTFIFO_EVT_IN_15 |
|
AASRC0_OUTFIFO_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_52 |
|
AASRC0_OUTFIFO_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_52 |
|
AASRC0_OUTFIFO_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_52 |
|
AASRC0_OUTFIFO_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_52 |
|
AASRC0_OUTFIFO_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_52 |
|
AASRC0_OUTFIFO_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_52 |
|
AASRC0_OUTGROUP_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_53 |
|
AASRC0_OUTGROUP_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_53 |
|
AASRC0_OUTGROUP_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_53 |
|
AASRC0_OUTGROUP_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_53 |
|
AASRC0_OUTGROUP_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_53 |
|
AASRC0_OUTGROUP_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_53 |
|
AASRC0_OUTGRP_DMA_OUT_0 |
PDMA_AASRC0_6_OUTGRP_EVT_IN_0 |
|
AASRC0_OUTGRP_DMA_OUT_1 |
PDMA_AASRC0_6_OUTGRP_EVT_IN_1 |
|
AASRC0_OUTGRP_DMA_OUT_2 |
PDMA_AASRC0_6_OUTGRP_EVT_IN_2 |
|
AASRC0_OUTGRP_DMA_OUT_3 |
PDMA_AASRC0_6_OUTGRP_EVT_IN_3 |
|
AASRC1_ERR_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_59 |
|
AASRC1_ERR_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_59 |
|
AASRC1_ERR_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_59 |
|
AASRC1_ERR_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_59 |
|
AASRC1_ERR_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_59 |
|
AASRC1_ERR_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_59 |
|
AASRC1_INFIFO_DMA_OUT_0 |
PDMA_AASRC1_7_INFIFO_EVT_IN_0 |
|
AASRC1_INFIFO_DMA_OUT_1 |
PDMA_AASRC1_7_INFIFO_EVT_IN_1 |
|
AASRC1_INFIFO_DMA_OUT_2 |
PDMA_AASRC1_7_INFIFO_EVT_IN_2 |
|
AASRC1_INFIFO_DMA_OUT_3 |
PDMA_AASRC1_7_INFIFO_EVT_IN_3 |
|
AASRC1_INFIFO_DMA_OUT_4 |
PDMA_AASRC1_7_INFIFO_EVT_IN_4 |
|
AASRC1_INFIFO_DMA_OUT_5 |
PDMA_AASRC1_7_INFIFO_EVT_IN_5 |
|
AASRC1_INFIFO_DMA_OUT_6 |
PDMA_AASRC1_7_INFIFO_EVT_IN_6 |
|
AASRC1_INFIFO_DMA_OUT_7 |
PDMA_AASRC1_7_INFIFO_EVT_IN_7 |
|
AASRC1_INFIFO_DMA_OUT_8 |
PDMA_AASRC1_7_INFIFO_EVT_IN_8 |
|
AASRC1_INFIFO_DMA_OUT_9 |
PDMA_AASRC1_7_INFIFO_EVT_IN_9 |
|
AASRC1_INFIFO_DMA_OUT_10 |
PDMA_AASRC1_7_INFIFO_EVT_IN_10 |
|
AASRC1_INFIFO_DMA_OUT_11 |
PDMA_AASRC1_7_INFIFO_EVT_IN_11 |
|
AASRC1_INFIFO_DMA_OUT_12 |
PDMA_AASRC1_7_INFIFO_EVT_IN_12 |
|
AASRC1_INFIFO_DMA_OUT_13 |
PDMA_AASRC1_7_INFIFO_EVT_IN_13 |
|
AASRC1_INFIFO_DMA_OUT_14 |
PDMA_AASRC1_7_INFIFO_EVT_IN_14 |
|
AASRC1_INFIFO_DMA_OUT_15 |
PDMA_AASRC1_7_INFIFO_EVT_IN_15 |
|
AASRC1_INFIFO_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_55 |
|
AASRC1_INFIFO_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_55 |
|
AASRC1_INFIFO_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_55 |
|
AASRC1_INFIFO_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_55 |
|
AASRC1_INFIFO_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_55 |
|
AASRC1_INFIFO_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_55 |
|
AASRC1_INGROUP_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_56 |
|
AASRC1_INGROUP_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_56 |
|
AASRC1_INGROUP_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_56 |
|
AASRC1_INGROUP_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_56 |
|
AASRC1_INGROUP_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_56 |
|
AASRC1_INGROUP_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_56 |
|
AASRC1_INGRP_DMA_OUT_0 |
PDMA_AASRC1_7_INGRP_EVT_IN_0 |
|
AASRC1_INGRP_DMA_OUT_1 |
PDMA_AASRC1_7_INGRP_EVT_IN_1 |
|
AASRC1_INGRP_DMA_OUT_2 |
PDMA_AASRC1_7_INGRP_EVT_IN_2 |
|
AASRC1_INGRP_DMA_OUT_3 |
PDMA_AASRC1_7_INGRP_EVT_IN_3 |
|
AASRC1_OUTFIFO_DMA_OUT_0 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_0 |
|
AASRC1_OUTFIFO_DMA_OUT_1 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_1 |
|
AASRC1_OUTFIFO_DMA_OUT_2 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_2 |
|
AASRC1_OUTFIFO_DMA_OUT_3 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_3 |
|
AASRC1_OUTFIFO_DMA_OUT_4 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_4 |
|
AASRC1_OUTFIFO_DMA_OUT_5 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_5 |
|
AASRC1_OUTFIFO_DMA_OUT_6 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_6 |
|
AASRC1_OUTFIFO_DMA_OUT_7 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_7 |
|
AASRC1_OUTFIFO_DMA_OUT_8 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_8 |
|
AASRC1_OUTFIFO_DMA_OUT_9 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_9 |
|
AASRC1_OUTFIFO_DMA_OUT_10 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_10 |
|
AASRC1_OUTFIFO_DMA_OUT_11 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_11 |
|
AASRC1_OUTFIFO_DMA_OUT_12 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_12 |
|
AASRC1_OUTFIFO_DMA_OUT_13 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_13 |
|
AASRC1_OUTFIFO_DMA_OUT_14 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_14 |
|
AASRC1_OUTFIFO_DMA_OUT_15 |
PDMA_AASRC1_7_OUTFIFO_EVT_IN_15 |
|
AASRC1_OUTFIFO_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_57 |
|
AASRC1_OUTFIFO_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_57 |
|
AASRC1_OUTFIFO_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_57 |
|
AASRC1_OUTFIFO_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_57 |
|
AASRC1_OUTFIFO_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_57 |
|
AASRC1_OUTFIFO_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_57 |
|
AASRC1_OUTGROUP_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_58 |
|
AASRC1_OUTGROUP_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_58 |
|
AASRC1_OUTGROUP_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_58 |
|
AASRC1_OUTGROUP_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_58 |
|
AASRC1_OUTGROUP_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_58 |
|
AASRC1_OUTGROUP_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_58 |
|
AASRC1_OUTGRP_DMA_OUT_0 |
PDMA_AASRC1_7_OUTGRP_EVT_IN_0 |
|
AASRC1_OUTGRP_DMA_OUT_1 |
PDMA_AASRC1_7_OUTGRP_EVT_IN_1 |
|
AASRC1_OUTGRP_DMA_OUT_2 |
PDMA_AASRC1_7_OUTGRP_EVT_IN_2 |
|
AASRC1_OUTGRP_DMA_OUT_3 |
PDMA_AASRC1_7_OUTGRP_EVT_IN_3 |
| OUT Interrupt | Connected To |
|---|---|
|
DDPA0_DDPA_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_177 |
|
DDPA0_DDPA_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_177 |
|
DDPA0_DDPA_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_177 |
|
DDPA0_DDPA_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_177 |
|
DDPA0_DDPA_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_177 |
|
DDPA0_DDPA_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_177 |
|
DDPA0_DDPA_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_177 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
EPWM0 |
EPWM0_EPWM_ETINT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_229 |
|
EPWM0_EPWM_ETINT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_229 |
|
|
EPWM0_EPWM_ETINT_OUT_0 |
R5FSS0_CORE0_INTR_IN_3 |
|
|
EPWM0_EPWM_ETINT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_123 |
|
|
EPWM0_EPWM_SYNCO_O_OUT_0 |
TIMESYNC_EVENT_INTROUTER0_IN_IN_9 |
|
|
EPWM0_EPWM_SYNCOUT_OUT_0 |
EPWM1_EPWM_SYNCIN_IN_0 |
|
|
EPWM0_EPWM_TRIPZINT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_230 |
|
|
EPWM0_EPWM_TRIPZINT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_230 |
|
|
EPWM0_EPWM_TRIPZINT_OUT_0 |
R5FSS0_CORE0_INTR_IN_80 |
|
|
EPWM0_EPWM_TRIPZINT_OUT_0 |
R5FSS0_CORE1_INTR_IN_80 |
|
|
EPWM0_EPWM_TRIPZINT_OUT_0 |
R5FSS1_CORE0_INTR_IN_80 |
|
|
EPWM0_EPWM_TRIPZINT_OUT_0 |
R5FSS1_CORE1_INTR_IN_80 |
|
|
EPWM0_EPWM_TRIPZINT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_124 |
|
|
EPWM1 |
EPWM1_EPWM_ETINT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_231 |
|
EPWM1_EPWM_ETINT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_231 |
|
|
EPWM1_EPWM_ETINT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_125 |
|
|
EPWM1_EPWM_SYNCOUT_OUT_0 |
EPWM2_EPWM_SYNCIN_IN_0 |
|
|
EPWM1_EPWM_TRIPZINT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_233 |
|
|
EPWM1_EPWM_TRIPZINT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_233 |
|
|
EPWM1_EPWM_TRIPZINT_OUT_0 |
R5FSS0_CORE0_INTR_IN_81 |
|
|
EPWM1_EPWM_TRIPZINT_OUT_0 |
R5FSS0_CORE1_INTR_IN_81 |
|
|
EPWM1_EPWM_TRIPZINT_OUT_0 |
R5FSS1_CORE0_INTR_IN_81 |
|
|
EPWM1_EPWM_TRIPZINT_OUT_0 |
R5FSS1_CORE1_INTR_IN_81 |
|
|
EPWM1_EPWM_TRIPZINT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_126 |
|
|
EPWM2 |
EPWM2_EPWM_ETINT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_234 |
|
EPWM2_EPWM_ETINT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_234 |
|
|
EPWM2_EPWM_ETINT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_127 |
|
|
EPWM2_EPWM_TRIPZINT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_235 |
|
|
EPWM2_EPWM_TRIPZINT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_235 |
|
|
EPWM2_EPWM_TRIPZINT_OUT_0 |
R5FSS0_CORE0_INTR_IN_82 |
|
|
EPWM2_EPWM_TRIPZINT_OUT_0 |
R5FSS0_CORE1_INTR_IN_82 |
|
|
EPWM2_EPWM_TRIPZINT_OUT_0 |
R5FSS1_CORE0_INTR_IN_82 |
|
|
EPWM2_EPWM_TRIPZINT_OUT_0 |
R5FSS1_CORE1_INTR_IN_82 |
|
|
EPWM2_EPWM_TRIPZINT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_148 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
PBIST0 |
PBIST0_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST0_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST0_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST0_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST0_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST0_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_228 |
|
|
PBIST0_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_228 |
|
|
PBIST0_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_228 |
|
|
PBIST0_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_157 |
|
|
PBIST1 |
PBIST1_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST1_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST1_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST1_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST1_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST1_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_243 |
|
|
PBIST1_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_243 |
|
|
PBIST1_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_243 |
|
|
PBIST1_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_213 |
|
|
PBIST2 |
PBIST2_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST2_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST2_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST2_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST2_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST2_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_244 |
|
|
PBIST2_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_244 |
|
|
PBIST2_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_244 |
|
|
PBIST2_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_214 |
|
|
PBIST3 |
PBIST3_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST3_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST3_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST3_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST3_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST3_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_246 |
|
|
PBIST3_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_246 |
|
|
PBIST3_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_246 |
|
|
PBIST3_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_202 |
|
|
PBIST4 |
PBIST4_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST4_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST4_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST4_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST4_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST4_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_247 |
|
|
PBIST4_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_247 |
|
|
PBIST4_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_247 |
|
|
PBIST4_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_203 |
|
|
PBIST5 |
PBIST5_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST5_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST5_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST5_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST5_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST5_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_248 |
|
|
PBIST5_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_248 |
|
|
PBIST5_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_248 |
|
|
PBIST5_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_204 |
|
|
PBIST6 |
PBIST6_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST6_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST6_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST6_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST6_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST6_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_249 |
|
|
PBIST6_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_249 |
|
|
PBIST6_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_249 |
|
|
PBIST6_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_205 |
|
|
PBIST7 |
PBIST7_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST7_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST7_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST7_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST7_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST7_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_250 |
|
|
PBIST7_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_250 |
|
|
PBIST7_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_250 |
|
|
PBIST7_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_206 |
|
|
PBIST8 |
PBIST8_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_113 |
|
PBIST8_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_113 |
|
|
PBIST8_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_113 |
|
|
PBIST8_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_113 |
|
|
PBIST8_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_113 |
|
|
PBIST8_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_251 |
|
|
PBIST8_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_251 |
|
|
PBIST8_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_251 |
|
|
PBIST8_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_207 |
|
|
WKUP_PBIST1 |
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_114 |
|
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_114 |
|
|
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_114 |
|
|
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_114 |
|
|
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_114 |
|
|
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_240 |
|
|
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_240 |
|
|
WKUP_PBIST1_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_240 |
|
|
WKUP_PBIST1_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_159 |
|
|
WKUP_PBIST0 |
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE0_INTR_IN_114 |
|
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
R5FSS0_CORE1_INTR_IN_114 |
|
|
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE0_INTR_IN_114 |
|
|
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
R5FSS1_CORE1_INTR_IN_114 |
|
|
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_114 |
|
|
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_234 |
|
|
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_234 |
|
|
WKUP_PBIST0_DFT_PBIST_CPU_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_234 |
|
|
WKUP_PBIST0_DFT_PBIST_SAFETY_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_158 |
| OUT Interrupt | Connected To |
|---|---|
|
WKUP_VTM0_CORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_11 |
|
WKUP_VTM0_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_139 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_183 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_183 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_8 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_137 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_183 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_183 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_183 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_183 |
|
WKUP_VTM0_THERM_LVL_GT_TH1_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_183 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_184 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_184 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_10 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_138 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_184 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_184 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_184 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_184 |
|
WKUP_VTM0_THERM_LVL_GT_TH2_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_184 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_185 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_185 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_9 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_136 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
R5FSS0_CORE0_INTR_IN_185 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
R5FSS0_CORE1_INTR_IN_185 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
R5FSS1_CORE0_INTR_IN_185 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
R5FSS1_CORE1_INTR_IN_185 |
|
WKUP_VTM0_THERM_LVL_LT_TH0_INTR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_185 |
|
WKUP_VTM0_UNCORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_12 |
|
WKUP_VTM0_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_140 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_240 |
|
MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_OUT_1 |
R5FSS0_CORE1_INTR_IN_240 |
|
|
MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_OUT_2 |
R5FSS1_CORE0_INTR_IN_240 |
|
|
MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_OUT_3 |
R5FSS1_CORE1_INTR_IN_240 |
|
|
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_241 |
|
MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_OUT_1 |
R5FSS1_CORE0_INTR_IN_241 |
|
|
MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_OUT_2 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_6 |
|
|
MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_OUT_3 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_6 |
|
|
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_241 |
|
MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_OUT_1 |
R5FSS1_CORE1_INTR_IN_241 |
|
|
MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_OUT_2 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_7 |
|
|
MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_OUT_3 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_7 |
|
|
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_242 |
|
MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_OUT_1 |
R5FSS0_CORE1_INTR_IN_242 |
|
|
MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_OUT_2 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_8 |
|
|
MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_OUT_3 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_8 |
|
|
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_242 |
|
MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_OUT_1 |
R5FSS1_CORE1_INTR_IN_242 |
|
|
MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_OUT_2 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_9 |
|
|
MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_OUT_3 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_9 |
|
|
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_240 |
|
MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_OUT_1 |
R5FSS0_CORE0_INTR_IN_243 |
|
|
MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_OUT_2 |
R5FSS1_CORE1_INTR_IN_243 |
|
|
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_241 |
|
MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_OUT_1 |
R5FSS0_CORE1_INTR_IN_243 |
|
|
MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_OUT_2 |
R5FSS1_CORE0_INTR_IN_243 |
|
|
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_242 |
|
MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_OUT_1 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_10 |
|
|
MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_OUT_2 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_10 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
MCAN0 |
MCAN0_MCANSS_ECC_CORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_58 |
|
MCAN0_MCANSS_ECC_UNCORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_59 |
|
|
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_186 |
|
|
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_186 |
|
|
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_186 |
|
|
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_186 |
|
|
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_186 |
|
|
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_186 |
|
|
MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_186 |
|
|
MCAN0_MCANSS_FE_OUT_0 |
PDMA0_MCANSS_MAIN_0_FE_IN_0 |
|
|
MCAN0_MCANSS_FE_OUT_1 |
PDMA0_MCANSS_MAIN_0_FE_IN_1 |
|
|
MCAN0_MCANSS_FE_OUT_2 |
PDMA0_MCANSS_MAIN_0_FE_IN_2 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_187 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_187 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_230 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_230 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_230 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_230 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_230 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_188 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_188 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE0_INTR_IN_231 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE1_INTR_IN_231 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE0_INTR_IN_231 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE1_INTR_IN_231 |
|
|
MCAN0_MCANSS_MCAN_LVL_INT_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_231 |
|
|
MCAN0_MCANSS_TX_DMA_OUT_0 |
PDMA0_MCANSS_MAIN_0_TX_IN_0 |
|
|
MCAN0_MCANSS_TX_DMA_OUT_1 |
PDMA0_MCANSS_MAIN_0_TX_IN_1 |
|
|
MCAN0_MCANSS_TX_DMA_OUT_2 |
PDMA0_MCANSS_MAIN_0_TX_IN_2 |
|
|
MCAN1 |
MCAN1_MCANSS_ECC_CORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_60 |
|
MCAN1_MCANSS_ECC_UNCORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_61 |
|
|
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_199 |
|
|
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_199 |
|
|
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_229 |
|
|
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_229 |
|
|
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_229 |
|
|
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_229 |
|
|
MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_229 |
|
|
MCAN1_MCANSS_FE_OUT_0 |
PDMA0_MCANSS_MAIN_1_FE_IN_0 |
|
|
MCAN1_MCANSS_FE_OUT_1 |
PDMA0_MCANSS_MAIN_1_FE_IN_1 |
|
|
MCAN1_MCANSS_FE_OUT_2 |
PDMA0_MCANSS_MAIN_1_FE_IN_2 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_245 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_245 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_232 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_232 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_232 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_232 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_232 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_246 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_246 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE0_INTR_IN_233 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE1_INTR_IN_233 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE0_INTR_IN_233 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE1_INTR_IN_233 |
|
|
MCAN1_MCANSS_MCAN_LVL_INT_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_233 |
|
|
MCAN1_MCANSS_TX_DMA_OUT_0 |
PDMA0_MCANSS_MAIN_1_TX_IN_0 |
|
|
MCAN1_MCANSS_TX_DMA_OUT_1 |
PDMA0_MCANSS_MAIN_1_TX_IN_1 |
|
|
MCAN1_MCANSS_TX_DMA_OUT_2 |
PDMA0_MCANSS_MAIN_1_TX_IN_2 |
|
|
MCAN2 |
MCAN2_MCANSS_ECC_CORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_62 |
|
MCAN2_MCANSS_ECC_UNCORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_63 |
|
|
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_189 |
|
|
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_189 |
|
|
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_187 |
|
|
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_187 |
|
|
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_187 |
|
|
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_187 |
|
|
MCAN2_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_187 |
|
|
MCAN2_MCANSS_FE_OUT_0 |
PDMA4_MCANSS_MAIN_2_FE_IN_0 |
|
|
MCAN2_MCANSS_FE_OUT_1 |
PDMA4_MCANSS_MAIN_2_FE_IN_1 |
|
|
MCAN2_MCANSS_FE_OUT_2 |
PDMA4_MCANSS_MAIN_2_FE_IN_2 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_247 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_247 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_234 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_234 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_234 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_234 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_234 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_248 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_248 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE0_INTR_IN_235 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE1_INTR_IN_235 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE0_INTR_IN_235 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE1_INTR_IN_235 |
|
|
MCAN2_MCANSS_MCAN_LVL_INT_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_235 |
|
|
MCAN2_MCANSS_TX_DMA_OUT_0 |
PDMA4_MCANSS_MAIN_2_TX_IN_0 |
|
|
MCAN2_MCANSS_TX_DMA_OUT_1 |
PDMA4_MCANSS_MAIN_2_TX_IN_1 |
|
|
MCAN2_MCANSS_TX_DMA_OUT_2 |
PDMA4_MCANSS_MAIN_2_TX_IN_2 |
|
|
MCAN3 |
MCAN3_MCANSS_ECC_CORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_68 |
|
MCAN3_MCANSS_ECC_UNCORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_69 |
|
|
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_190 |
|
|
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_190 |
|
|
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_188 |
|
|
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_188 |
|
|
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_188 |
|
|
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_188 |
|
|
MCAN3_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_188 |
|
|
MCAN3_MCANSS_FE_OUT_0 |
PDMA4_MCANSS_MAIN_3_FE_IN_0 |
|
|
MCAN3_MCANSS_FE_OUT_1 |
PDMA4_MCANSS_MAIN_3_FE_IN_1 |
|
|
MCAN3_MCANSS_FE_OUT_2 |
PDMA4_MCANSS_MAIN_3_FE_IN_2 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_249 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_249 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_236 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_236 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_236 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_236 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_236 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_250 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_250 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE0_INTR_IN_237 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE1_INTR_IN_237 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE0_INTR_IN_237 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE1_INTR_IN_237 |
|
|
MCAN3_MCANSS_MCAN_LVL_INT_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_237 |
|
|
MCAN3_MCANSS_TX_DMA_OUT_0 |
PDMA4_MCANSS_MAIN_3_TX_IN_0 |
|
|
MCAN3_MCANSS_TX_DMA_OUT_1 |
PDMA4_MCANSS_MAIN_3_TX_IN_1 |
|
|
MCAN3_MCANSS_TX_DMA_OUT_2 |
PDMA4_MCANSS_MAIN_3_TX_IN_2 |
|
|
MCAN4 |
MCAN4_MCANSS_ECC_CORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_70 |
|
MCAN4_MCANSS_ECC_UNCORR_LVL_INT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_71 |
|
|
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_191 |
|
|
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_191 |
|
|
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_189 |
|
|
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_189 |
|
|
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_189 |
|
|
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_189 |
|
|
MCAN4_MCANSS_EXT_TS_ROLLOVER_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_189 |
|
|
MCAN4_MCANSS_FE_OUT_0 |
PDMA4_MCANSS_MAIN_4_FE_IN_0 |
|
|
MCAN4_MCANSS_FE_OUT_1 |
PDMA4_MCANSS_MAIN_4_FE_IN_1 |
|
|
MCAN4_MCANSS_FE_OUT_2 |
PDMA4_MCANSS_MAIN_4_FE_IN_2 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_251 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_251 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_238 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_238 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_238 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_238 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_238 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_252 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_252 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE0_INTR_IN_239 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS0_CORE1_INTR_IN_239 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE0_INTR_IN_239 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
R5FSS1_CORE1_INTR_IN_239 |
|
|
MCAN4_MCANSS_MCAN_LVL_INT_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_239 |
|
|
MCAN4_MCANSS_TX_DMA_OUT_0 |
PDMA4_MCANSS_MAIN_4_TX_IN_0 |
|
|
MCAN4_MCANSS_TX_DMA_OUT_1 |
PDMA4_MCANSS_MAIN_4_TX_IN_1 |
|
|
MCAN4_MCANSS_TX_DMA_OUT_2 |
PDMA4_MCANSS_MAIN_4_TX_IN_2 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
MCASP0 |
MCASP0_REC_DMA_EVENT_REQ_OUT_0 |
PDMA2_MCASP_MAIN_0_RX_IN_0 |
|
MCASP0_REC_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_267 |
|
|
MCASP0_REC_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_267 |
|
|
MCASP0_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_120 |
|
|
MCASP0_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_120 |
|
|
MCASP0_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_120 |
|
|
MCASP0_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_120 |
|
|
MCASP0_XMIT_DMA_EVENT_REQ_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_1 |
|
|
MCASP0_XMIT_DMA_EVENT_REQ_OUT_0 |
PDMA2_MCASP_MAIN_0_TX_IN_0 |
|
|
MCASP0_XMIT_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_268 |
|
|
MCASP0_XMIT_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_268 |
|
|
MCASP0_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_121 |
|
|
MCASP0_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_121 |
|
|
MCASP0_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_121 |
|
|
MCASP0_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_121 |
|
|
MCASP1 |
MCASP1_REC_DMA_EVENT_REQ_OUT_0 |
PDMA2_MCASP_MAIN_1_RX_IN_0 |
|
MCASP1_REC_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_269 |
|
|
MCASP1_REC_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_269 |
|
|
MCASP1_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_122 |
|
|
MCASP1_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_122 |
|
|
MCASP1_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_122 |
|
|
MCASP1_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_122 |
|
|
MCASP1_XMIT_DMA_EVENT_REQ_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_2 |
|
|
MCASP1_XMIT_DMA_EVENT_REQ_OUT_0 |
PDMA2_MCASP_MAIN_1_TX_IN_0 |
|
|
MCASP1_XMIT_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_270 |
|
|
MCASP1_XMIT_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_270 |
|
|
MCASP1_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_123 |
|
|
MCASP1_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_123 |
|
|
MCASP1_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_123 |
|
|
MCASP1_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_123 |
|
|
MCASP2 |
MCASP2_REC_DMA_EVENT_REQ_OUT_0 |
PDMA2_MCASP_MAIN_2_RX_IN_0 |
|
MCASP2_REC_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_271 |
|
|
MCASP2_REC_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_271 |
|
|
MCASP2_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_124 |
|
|
MCASP2_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_124 |
|
|
MCASP2_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_124 |
|
|
MCASP2_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_124 |
|
|
MCASP2_XMIT_DMA_EVENT_REQ_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_3 |
|
|
MCASP2_XMIT_DMA_EVENT_REQ_OUT_0 |
PDMA2_MCASP_MAIN_2_TX_IN_0 |
|
|
MCASP2_XMIT_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_272 |
|
|
MCASP2_XMIT_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_272 |
|
|
MCASP2_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_125 |
|
|
MCASP2_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_125 |
|
|
MCASP2_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_125 |
|
|
MCASP2_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_125 |
|
|
MCASP3 |
MCASP3_REC_DMA_EVENT_REQ_OUT_0 |
PDMA3_MCASP_MAIN_3_RX_IN_0 |
|
MCASP3_REC_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_273 |
|
|
MCASP3_REC_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_273 |
|
|
MCASP3_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_126 |
|
|
MCASP3_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_126 |
|
|
MCASP3_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_126 |
|
|
MCASP3_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_126 |
|
|
MCASP3_XMIT_DMA_EVENT_REQ_OUT_0 |
PDMA3_MCASP_MAIN_3_TX_IN_0 |
|
|
MCASP3_XMIT_DMA_EVENT_REQ_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_4 |
|
|
MCASP3_XMIT_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_274 |
|
|
MCASP3_XMIT_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_274 |
|
|
MCASP3_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_127 |
|
|
MCASP3_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_127 |
|
|
MCASP3_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_127 |
|
|
MCASP3_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_127 |
|
|
MCASP4 |
MCASP4_REC_DMA_EVENT_REQ_OUT_0 |
PDMA3_MCASP_MAIN_4_RX_IN_0 |
|
MCASP4_REC_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_275 |
|
|
MCASP4_REC_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_275 |
|
|
MCASP4_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_130 |
|
|
MCASP4_REC_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_130 |
|
|
MCASP4_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_130 |
|
|
MCASP4_REC_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_130 |
|
|
MCASP4_XMIT_DMA_EVENT_REQ_OUT_0 |
PDMA3_MCASP_MAIN_4_TX_IN_0 |
|
|
MCASP4_XMIT_DMA_EVENT_REQ_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_5 |
|
|
MCASP4_XMIT_INTR_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_276 |
|
|
MCASP4_XMIT_INTR_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_276 |
|
|
MCASP4_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_131 |
|
|
MCASP4_XMIT_INTR_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_131 |
|
|
MCASP4_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_131 |
|
|
MCASP4_XMIT_INTR_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_131 |
| OUT Interrupt | Connected To |
|---|---|
|
MCRC64_0_DMA_EVENT_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_28 |
|
MCRC64_0_DMA_EVENT_OUT_1 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_29 |
|
MCRC64_0_DMA_EVENT_OUT_2 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_30 |
|
MCRC64_0_DMA_EVENT_OUT_3 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_31 |
|
MCRC64_0_INT_MCRC_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_166 |
|
MCRC64_0_INT_MCRC_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_166 |
|
MCRC64_0_INT_MCRC_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_7 |
|
MCRC64_0_INT_MCRC_OUT_0 |
R5FSS0_CORE0_INTR_IN_119 |
|
MCRC64_0_INT_MCRC_OUT_0 |
R5FSS0_CORE1_INTR_IN_119 |
|
MCRC64_0_INT_MCRC_OUT_0 |
R5FSS1_CORE0_INTR_IN_119 |
|
MCRC64_0_INT_MCRC_OUT_0 |
R5FSS1_CORE1_INTR_IN_119 |
|
MCRC64_0_INT_MCRC_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_119 |
| OUT Interrupt | Connected To |
|---|---|
|
MLB0_MLBSS_ECC_CORR_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_77 |
|
MLB0_MLBSS_ECC_UNCORR_LVL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_78 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_61 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_61 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_61 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_61 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_61 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_61 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_62 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_62 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
R5FSS0_CORE0_INTR_IN_62 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
R5FSS0_CORE1_INTR_IN_62 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
R5FSS1_CORE0_INTR_IN_62 |
|
MLB0_MLBSS_MLB_AHB_INT_OUT_1 |
R5FSS1_CORE1_INTR_IN_62 |
|
MLB0_MLBSS_MLB_INT_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_60 |
|
MLB0_MLBSS_MLB_INT_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_60 |
|
MLB0_MLBSS_MLB_INT_OUT_0 |
R5FSS0_CORE0_INTR_IN_60 |
|
MLB0_MLBSS_MLB_INT_OUT_0 |
R5FSS0_CORE1_INTR_IN_60 |
|
MLB0_MLBSS_MLB_INT_OUT_0 |
R5FSS1_CORE0_INTR_IN_60 |
|
MLB0_MLBSS_MLB_INT_OUT_0 |
R5FSS1_CORE1_INTR_IN_60 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
I2C0 |
I2C0_POINTRPEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_193 |
|
I2C0_POINTRPEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_193 |
|
|
I2C0_POINTRPEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_193 |
|
|
I2C0_POINTRPEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_193 |
|
|
I2C0_POINTRPEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_193 |
|
|
I2C0_POINTRPEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_193 |
|
|
I2C0_POINTRPEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_193 |
|
|
I2C1 |
I2C1_POINTRPEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_194 |
|
I2C1_POINTRPEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_194 |
|
|
I2C1_POINTRPEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_194 |
|
|
I2C1_POINTRPEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_194 |
|
|
I2C1_POINTRPEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_194 |
|
|
I2C1_POINTRPEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_194 |
|
|
I2C1_POINTRPEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_194 |
|
|
I2C2 |
I2C2_POINTRPEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_195 |
|
I2C2_POINTRPEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_195 |
|
|
I2C2_POINTRPEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_195 |
|
|
I2C2_POINTRPEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_195 |
|
|
I2C2_POINTRPEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_195 |
|
|
I2C2_POINTRPEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_195 |
|
|
I2C2_POINTRPEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_195 |
|
|
I2C3 |
I2C3_POINTRPEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_196 |
|
I2C3_POINTRPEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_196 |
|
|
I2C3_POINTRPEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_196 |
|
|
I2C3_POINTRPEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_196 |
|
|
I2C3_POINTRPEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_196 |
|
|
I2C3_POINTRPEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_196 |
|
|
I2C3_POINTRPEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_196 |
|
|
I2C4 |
I2C4_POINTRPEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_197 |
|
I2C4_POINTRPEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_197 |
|
|
I2C4_POINTRPEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_197 |
|
|
I2C4_POINTRPEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_197 |
|
|
I2C4_POINTRPEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_197 |
|
|
I2C5 |
I2C5_POINTRPEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_198 |
|
I2C5_POINTRPEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_198 |
|
|
I2C5_POINTRPEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_198 |
|
|
I2C5_POINTRPEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_198 |
|
|
I2C5_POINTRPEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_198 |
|
|
I2C6 |
I2C6_POINTRPEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_199 |
|
I2C6_POINTRPEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_199 |
|
|
I2C6_POINTRPEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_199 |
|
|
I2C6_POINTRPEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_199 |
|
|
I2C6_POINTRPEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_199 |
|
|
WKUP_I2C0 |
WKUP_I2C0_CLKSTOP_WAKEUP_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_143 |
|
WKUP_I2C0_POINTRPEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_197 |
|
|
WKUP_I2C0_POINTRPEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_197 |
|
|
WKUP_I2C0_POINTRPEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_190 |
|
|
WKUP_I2C0_POINTRPEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_190 |
|
|
WKUP_I2C0_POINTRPEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_190 |
|
|
WKUP_I2C0_POINTRPEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_190 |
|
|
WKUP_I2C0_POINTRPEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_190 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
MSRAM_1MB0 |
MSRAM_1MB0_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_184 |
|
MSRAM_1MB0_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_185 |
|
|
MSRAM_1MB1 |
MSRAM_1MB1_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_186 |
|
MSRAM_1MB1_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_187 |
|
|
MSRAM_1MB2 |
MSRAM_1MB2_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_188 |
|
MSRAM_1MB2_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_189 |
|
|
MSRAM_1MB3 |
MSRAM_1MB3_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_190 |
|
MSRAM_1MB3_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_191 |
|
|
MSRAM_1MB4 |
MSRAM_1MB4_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_215 |
|
MSRAM_1MB4_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_216 |
|
|
MSRAM_1MB5 |
MSRAM_1MB5_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_217 |
|
MSRAM_1MB5_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_218 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
pllfracf2_ssmod_16fft0 |
PLLFRACF2_SSMOD_16FFT0_LOCKLOSS_IPCFG_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_54 |
|
PLLFRACF2_SSMOD_16FFT0_LOCKLOSS_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_128 |
|
|
pllfracf2_ssmod_16fft1 |
PLLFRACF2_SSMOD_16FFT1_LOCKLOSS_IPCFG_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_55 |
|
PLLFRACF2_SSMOD_16FFT1_LOCKLOSS_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_129 |
|
|
pllfracf2_ssmod_16fft14 |
PLLFRACF2_SSMOD_16FFT14_LOCKLOSS_IPCFG_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_58 |
|
PLLFRACF2_SSMOD_16FFT14_LOCKLOSS_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_132 |
|
|
pllfracf2_ssmod_16fft15 |
PLLFRACF2_SSMOD_16FFT15_LOCKLOSS_IPCFG_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_59 |
|
PLLFRACF2_SSMOD_16FFT15_LOCKLOSS_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_133 |
|
|
pllfracf2_ssmod_16fft2 |
PLLFRACF2_SSMOD_16FFT2_LOCKLOSS_IPCFG_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_56 |
|
PLLFRACF2_SSMOD_16FFT2_LOCKLOSS_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_130 |
|
|
pllfracf2_ssmod_16fft4 |
PLLFRACF2_SSMOD_16FFT4_LOCKLOSS_IPCFG_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_57 |
|
PLLFRACF2_SSMOD_16FFT4_LOCKLOSS_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_131 |
|
|
pllfracf2_ssmod_16fft7 |
PLLFRACF2_SSMOD_16FFT7_LOCKLOSS_IPCFG_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_61 |
|
PLLFRACF2_SSMOD_16FFT7_LOCKLOSS_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_18 |
|
|
MCU_pllfracf2_ssmod_16fft0 |
MCU_PLLFRACF2_SSMOD_16FFT0_LOCKLOSS_IPCFG_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_63 |
|
MCU_PLLFRACF2_SSMOD_16FFT0_LOCKLOSS_IPCFG_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_134 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
PSRAMECC0 |
PSRAMECC0_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_29 |
|
PSRAMECC0_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_90 |
|
|
WKUP_psram2kx32e0 |
WKUP_PSRAM2KX32E0_ECC_CORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_44 |
|
WKUP_PSRAM2KX32E0_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_16 |
|
|
WKUP_PSRAM2KX32E0_ECC_UNCORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_45 |
|
|
WKUP_PSRAM2KX32E0_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_17 |
|
|
WKUP_PSRAMECC_8K0 |
WKUP_PSRAMECC_8K0_ECC_CORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_42 |
|
WKUP_PSRAMECC_8K0_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_8 |
|
|
WKUP_PSRAMECC_8K0_ECC_UNCORR_LEVEL_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_43 |
|
|
WKUP_PSRAMECC_8K0_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_13 |
| OUT Interrupt | Connected To |
|---|---|
|
RL2_0_ERR_LVL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_261 |
|
RL2_0_ERR_LVL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_261 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_90 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_49 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_90 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_90 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_90 |
|
RL2_0_ERR_LVL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_261 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_90 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_49 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_90 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_90 |
|
RL2_0_ERR_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_90 |
| RL2_2_ERR_LVL_OUT_0 |
RL2_2_ERR_LVL_OUT_0 |
| RL2_2_ERR_LVL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_262 |
| RL2_2_ERR_LVL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_262 |
| RL2_2_ERR_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_91 |
| RL2_2_ERR_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_91 |
| RL2_2_ERR_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_49 |
| RL2_2_ERR_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_91 |
|
RL2_3_ERR_LVL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_263 |
|
RL2_3_ERR_LVL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_263 |
|
RL2_3_ERR_LVL_OUT_0 |
R5FSS0_CORE0_INTR_IN_92 |
|
RL2_3_ERR_LVL_OUT_0 |
R5FSS0_CORE1_INTR_IN_92 |
|
RL2_3_ERR_LVL_OUT_0 |
R5FSS1_CORE0_INTR_IN_92 |
|
RL2_3_ERR_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_49 |
|
RL2_3_ERR_LVL_OUT_0 |
R5FSS1_CORE1_INTR_IN_92 |
| OUT Interrupt | Connected To |
|---|---|
|
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_132 |
|
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_132 |
|
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
R5FSS0_CORE0_INTR_IN_97 |
|
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
R5FSS0_CORE1_INTR_IN_97 |
|
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
R5FSS1_CORE0_INTR_IN_97 |
|
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
R5FSS1_CORE1_INTR_IN_97 |
|
WKUP_RTCSS0_RTC_EVENT_PEND_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_97 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
RTI4 |
RTI4_INTR_WWD_OUT_0 |
C7X256V0_CLEC_SOC_EVENTS_IN_IN_4 |
|
RTI4_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_252 |
|
|
RTI4_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_252 |
|
|
RTI4_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_252 |
|
|
RTI5 |
RTI5_INTR_WWD_OUT_0 |
C7X256V1_CLEC_SOC_EVENTS_IN_IN_4 |
|
RTI5_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_253 |
|
|
RTI5_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_253 |
|
|
RTI5_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_253 |
|
|
RTI0 |
RTI0_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_224 |
|
RTI0_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_224 |
|
|
RTI0_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_224 |
|
|
RTI0_INTR_WWD_OUT_0 |
R5FSS0_CORE0_INTR_IN_30 |
|
|
RTI1 |
RTI1_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_225 |
|
RTI1_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_225 |
|
|
RTI1_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_225 |
|
|
RTI1_INTR_WWD_OUT_0 |
R5FSS0_CORE1_INTR_IN_30 |
|
|
RTI2 |
RTI2_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_241 |
|
RTI2_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_241 |
|
|
RTI2_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_241 |
|
|
RTI2_INTR_WWD_OUT_0 |
R5FSS1_CORE0_INTR_IN_30 |
|
|
RTI3 |
RTI3_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_242 |
|
RTI3_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_242 |
|
|
RTI3_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_242 |
|
|
RTI3_INTR_WWD_OUT_0 |
R5FSS1_CORE1_INTR_IN_30 |
|
|
WKUP_RTI0 |
WKUP_RTI0_INTR_WWD_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_86 |
|
WKUP_RTI0_INTR_WWD_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_86 |
|
|
WKUP_RTI0_INTR_WWD_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_86 |
|
|
WKUP_RTI0_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT0_IN_227 |
|
|
WKUP_RTI0_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT1_IN_227 |
|
|
WKUP_RTI0_INTR_WWD_OUT_0 |
ESM0_ESM_PLS_EVENT2_IN_227 |
|
|
WKUP_RTI0_INTR_WWD_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_30 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
SA3_SS0_DMSS_ECCAGGR_0 |
SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_DED_PEND_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_118 |
|
SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_SEC_PEND_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_119 |
|
|
SA3_SS0_INTAGGR_0 |
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_4 |
C7X256V0_CLEC_GIC_SPI_IN_112 |
|
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_4 |
C7X256V1_CLEC_GIC_SPI_IN_112 |
|
|
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_5 |
C7X256V0_CLEC_GIC_SPI_IN_113 |
|
|
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_5 |
C7X256V1_CLEC_GIC_SPI_IN_113 |
|
|
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_6 |
WKUP_R5FSS0_CORE0_INTR_IN_7 |
|
|
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_7 |
R5FSS0_CORE0_INTR_IN_7 |
|
|
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_7 |
R5FSS0_CORE1_INTR_IN_7 |
|
|
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_7 |
R5FSS1_CORE0_INTR_IN_7 |
|
|
SA3_SS0_INTAGGR_0_INTAGGR_VINTR_OUT_7 |
R5FSS1_CORE1_INTR_IN_7 |
|
|
SA3_SS0_SA_UL_0 |
SA3_SS0_SA_UL_0_SA_UL_ECC_CORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_120 |
|
SA3_SS0_SA_UL_0_SA_UL_ECC_UNCORR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_121 |
|
|
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_160 |
|
|
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_160 |
|
|
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
R5FSS0_CORE0_INTR_IN_16 |
|
|
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
R5FSS0_CORE1_INTR_IN_16 |
|
|
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
R5FSS1_CORE0_INTR_IN_16 |
|
|
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
R5FSS1_CORE1_INTR_IN_16 |
|
|
SA3_SS0_SA_UL_0_SA_UL_PKA_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_16 |
|
|
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_161 |
|
|
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_161 |
|
|
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
R5FSS0_CORE0_INTR_IN_17 |
|
|
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
R5FSS0_CORE1_INTR_IN_17 |
|
|
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
R5FSS1_CORE0_INTR_IN_17 |
|
|
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
R5FSS1_CORE1_INTR_IN_17 |
|
|
SA3_SS0_SA_UL_0_SA_UL_TRNG_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_17 |
| OUT Interrupt | Connected To |
|---|---|
|
EFUSE0_EFC_ERROR_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_131 |
|
EFUSE0_EFC_ERROR_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_131 |
|
EFUSE0_EFC_ERROR_OUT_0 |
WKUP_ESM0_ESM_LVL_EVENT_IN_25 |
|
EFUSE0_EFC_ERROR_OUT_0 |
R5FSS0_CORE0_INTR_IN_98 |
|
EFUSE0_EFC_ERROR_OUT_0 |
R5FSS0_CORE1_INTR_IN_98 |
|
EFUSE0_EFC_ERROR_OUT_0 |
R5FSS1_CORE0_INTR_IN_98 |
|
EFUSE0_EFC_ERROR_OUT_0 |
R5FSS1_CORE1_INTR_IN_98 |
|
EFUSE0_EFC_ERROR_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_98 |
| OUT Interrupt | Connected To |
|---|---|
|
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_201 |
|
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_201 |
|
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_201 |
|
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_201 |
|
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_201 |
|
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_201 |
|
DEBUGSS0_AQCMPINTR_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_201 |
|
DEBUGSS0_CTM_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_202 |
|
DEBUGSS0_CTM_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_202 |
|
DEBUGSS0_CTM_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_202 |
|
DEBUGSS0_CTM_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_202 |
|
DEBUGSS0_CTM_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_202 |
|
DEBUGSS0_CTM_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_202 |
|
DEBUGSS0_CTM_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_202 |
|
DEBUGSS0_DAVDMA_LEVEL_OUT_0 |
DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IN_27 |
|
DEBUGSS0_DAVDMA_LEVEL_OUT_0 |
USB0_TRACE_INEP_PKT_BUFF_AVAIL_IN_0 |
| OUT Interrupt | Connected To |
|---|---|
|
WKUP_PSC0_PSC_ALLINT_OUT_0 |
R5FSS0_CORE0_INTR_IN_145 |
|
WKUP_PSC0_PSC_ALLINT_OUT_0 |
R5FSS0_CORE1_INTR_IN_145 |
|
WKUP_PSC0_PSC_ALLINT_OUT_0 |
R5FSS1_CORE0_INTR_IN_145 |
|
WKUP_PSC0_PSC_ALLINT_OUT_0 |
R5FSS1_CORE1_INTR_IN_145 |
|
WKUP_PSC0_PSC_ALLINT_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_145 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
MCU_PRG_MCU_5POKS0 |
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_64 |
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_64 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_64 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_65 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_65 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_65 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_66 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_66 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_66 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_69 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_69 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_69 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_70 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_70 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_OV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_70 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_71 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_71 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_71 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_72 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_72 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_72 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_73 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_73 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_73 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_76 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_76 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_76 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_77 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_77 |
|
|
MCU_PRG_MCU_5POKS0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_77 |
|
|
MCU_PRG_MCU0 |
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_78 |
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_78 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_0 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_78 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_79 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_79 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_1 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_79 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_80 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_80 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_2 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_80 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_81 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_81 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_3 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_81 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT0_IN_82 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT1_IN_82 |
|
|
MCU_PRG_MCU0_POK_PGOOD_UV_OUT_N_TO_ESM_OUT_4 |
WKUP_ESM0_ESM_PLS_EVENT2_IN_82 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
MCSPI0 |
MCSPI0_DMA_READ_EVENT_OUT_0 |
PDMA0_SPI_MAIN_0_RX_IN_0 |
|
MCSPI0_DMA_READ_EVENT_OUT_1 |
PDMA0_SPI_MAIN_0_RX_IN_1 |
|
|
MCSPI0_DMA_READ_EVENT_OUT_2 |
PDMA0_SPI_MAIN_0_RX_IN_2 |
|
|
MCSPI0_DMA_READ_EVENT_OUT_3 |
PDMA0_SPI_MAIN_0_RX_IN_3 |
|
|
MCSPI0_DMA_WRITE_EVENT_OUT_0 |
PDMA0_SPI_MAIN_0_TX_IN_0 |
|
|
MCSPI0_DMA_WRITE_EVENT_OUT_1 |
PDMA0_SPI_MAIN_0_TX_IN_1 |
|
|
MCSPI0_DMA_WRITE_EVENT_OUT_2 |
PDMA0_SPI_MAIN_0_TX_IN_2 |
|
|
MCSPI0_DMA_WRITE_EVENT_OUT_3 |
PDMA0_SPI_MAIN_0_TX_IN_3 |
|
|
MCSPI0_INTR_SPI_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_204 |
|
|
MCSPI0_INTR_SPI_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_204 |
|
|
MCSPI0_INTR_SPI_OUT_0 |
R5FSS0_CORE0_INTR_IN_204 |
|
|
MCSPI0_INTR_SPI_OUT_0 |
R5FSS0_CORE1_INTR_IN_204 |
|
|
MCSPI0_INTR_SPI_OUT_0 |
R5FSS1_CORE0_INTR_IN_204 |
|
|
MCSPI0_INTR_SPI_OUT_0 |
R5FSS1_CORE1_INTR_IN_204 |
|
|
MCSPI0_INTR_SPI_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_204 |
|
|
MCSPI1 |
MCSPI1_DMA_READ_EVENT_OUT_0 |
PDMA0_SPI_MAIN_1_RX_IN_0 |
|
MCSPI1_DMA_READ_EVENT_OUT_1 |
PDMA0_SPI_MAIN_1_RX_IN_1 |
|
|
MCSPI1_DMA_READ_EVENT_OUT_2 |
PDMA0_SPI_MAIN_1_RX_IN_2 |
|
|
MCSPI1_DMA_READ_EVENT_OUT_3 |
PDMA0_SPI_MAIN_1_RX_IN_3 |
|
|
MCSPI1_DMA_WRITE_EVENT_OUT_0 |
PDMA0_SPI_MAIN_1_TX_IN_0 |
|
|
MCSPI1_DMA_WRITE_EVENT_OUT_1 |
PDMA0_SPI_MAIN_1_TX_IN_1 |
|
|
MCSPI1_DMA_WRITE_EVENT_OUT_2 |
PDMA0_SPI_MAIN_1_TX_IN_2 |
|
|
MCSPI1_DMA_WRITE_EVENT_OUT_3 |
PDMA0_SPI_MAIN_1_TX_IN_3 |
|
|
MCSPI1_INTR_SPI_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_205 |
|
|
MCSPI1_INTR_SPI_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_205 |
|
|
MCSPI1_INTR_SPI_OUT_0 |
R5FSS0_CORE0_INTR_IN_205 |
|
|
MCSPI1_INTR_SPI_OUT_0 |
R5FSS0_CORE1_INTR_IN_205 |
|
|
MCSPI1_INTR_SPI_OUT_0 |
R5FSS1_CORE0_INTR_IN_205 |
|
|
MCSPI1_INTR_SPI_OUT_0 |
R5FSS1_CORE1_INTR_IN_205 |
|
|
MCSPI1_INTR_SPI_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_205 |
|
|
MCSPI2 |
MCSPI2_DMA_READ_EVENT_OUT_0 |
PDMA0_SPI_MAIN_2_RX_IN_0 |
|
MCSPI2_DMA_READ_EVENT_OUT_1 |
PDMA0_SPI_MAIN_2_RX_IN_1 |
|
|
MCSPI2_DMA_READ_EVENT_OUT_2 |
PDMA0_SPI_MAIN_2_RX_IN_2 |
|
|
MCSPI2_DMA_READ_EVENT_OUT_3 |
PDMA0_SPI_MAIN_2_RX_IN_3 |
|
|
MCSPI2_DMA_WRITE_EVENT_OUT_0 |
PDMA0_SPI_MAIN_2_TX_IN_0 |
|
|
MCSPI2_DMA_WRITE_EVENT_OUT_1 |
PDMA0_SPI_MAIN_2_TX_IN_1 |
|
|
MCSPI2_DMA_WRITE_EVENT_OUT_2 |
PDMA0_SPI_MAIN_2_TX_IN_2 |
|
|
MCSPI2_DMA_WRITE_EVENT_OUT_3 |
PDMA0_SPI_MAIN_2_TX_IN_3 |
|
|
MCSPI2_INTR_SPI_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_206 |
|
|
MCSPI2_INTR_SPI_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_206 |
|
|
MCSPI2_INTR_SPI_OUT_0 |
R5FSS0_CORE0_INTR_IN_206 |
|
|
MCSPI2_INTR_SPI_OUT_0 |
R5FSS0_CORE1_INTR_IN_206 |
|
|
MCSPI2_INTR_SPI_OUT_0 |
R5FSS1_CORE0_INTR_IN_206 |
|
|
MCSPI2_INTR_SPI_OUT_0 |
R5FSS1_CORE1_INTR_IN_206 |
|
|
MCSPI2_INTR_SPI_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_206 |
|
|
MCSPI3 |
MCSPI3_DMA_READ_EVENT_OUT_0 |
PDMA4_SPI_MAIN_3_RX_IN_0 |
|
MCSPI3_DMA_READ_EVENT_OUT_1 |
PDMA4_SPI_MAIN_3_RX_IN_1 |
|
|
MCSPI3_DMA_READ_EVENT_OUT_2 |
PDMA4_SPI_MAIN_3_RX_IN_2 |
|
|
MCSPI3_DMA_READ_EVENT_OUT_3 |
PDMA4_SPI_MAIN_3_RX_IN_3 |
|
|
MCSPI3_DMA_WRITE_EVENT_OUT_0 |
PDMA4_SPI_MAIN_3_TX_IN_0 |
|
|
MCSPI3_DMA_WRITE_EVENT_OUT_1 |
PDMA4_SPI_MAIN_3_TX_IN_1 |
|
|
MCSPI3_DMA_WRITE_EVENT_OUT_2 |
PDMA4_SPI_MAIN_3_TX_IN_2 |
|
|
MCSPI3_DMA_WRITE_EVENT_OUT_3 |
PDMA4_SPI_MAIN_3_TX_IN_3 |
|
|
MCSPI3_INTR_SPI_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_207 |
|
|
MCSPI3_INTR_SPI_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_207 |
|
|
MCSPI3_INTR_SPI_OUT_0 |
R5FSS0_CORE0_INTR_IN_207 |
|
|
MCSPI3_INTR_SPI_OUT_0 |
R5FSS0_CORE1_INTR_IN_207 |
|
|
MCSPI3_INTR_SPI_OUT_0 |
R5FSS1_CORE0_INTR_IN_207 |
|
|
MCSPI3_INTR_SPI_OUT_0 |
R5FSS1_CORE1_INTR_IN_207 |
|
|
MCSPI3_INTR_SPI_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_207 |
|
|
MCSPI4 |
MCSPI4_DMA_READ_EVENT_OUT_0 |
PDMA4_SPI_MAIN_4_RX_IN_0 |
|
MCSPI4_DMA_READ_EVENT_OUT_1 |
PDMA4_SPI_MAIN_4_RX_IN_1 |
|
|
MCSPI4_DMA_READ_EVENT_OUT_2 |
PDMA4_SPI_MAIN_4_RX_IN_2 |
|
|
MCSPI4_DMA_READ_EVENT_OUT_3 |
PDMA4_SPI_MAIN_4_RX_IN_3 |
|
|
MCSPI4_DMA_WRITE_EVENT_OUT_0 |
PDMA4_SPI_MAIN_4_TX_IN_0 |
|
|
MCSPI4_DMA_WRITE_EVENT_OUT_1 |
PDMA4_SPI_MAIN_4_TX_IN_1 |
|
|
MCSPI4_DMA_WRITE_EVENT_OUT_2 |
PDMA4_SPI_MAIN_4_TX_IN_2 |
|
|
MCSPI4_DMA_WRITE_EVENT_OUT_3 |
PDMA4_SPI_MAIN_4_TX_IN_3 |
|
|
MCSPI4_INTR_SPI_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_208 |
|
|
MCSPI4_INTR_SPI_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_208 |
|
|
MCSPI4_INTR_SPI_OUT_0 |
R5FSS0_CORE0_INTR_IN_208 |
|
|
MCSPI4_INTR_SPI_OUT_0 |
R5FSS0_CORE1_INTR_IN_208 |
|
|
MCSPI4_INTR_SPI_OUT_0 |
R5FSS1_CORE0_INTR_IN_208 |
|
|
MCSPI4_INTR_SPI_OUT_0 |
R5FSS1_CORE1_INTR_IN_208 |
|
|
MCSPI4_INTR_SPI_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_208 |
| Instance | OUT Interrupt | Connected To |
|---|---|---|
|
UART0 |
UART0_USART_DMA_OUT_0 |
PDMA1_USART_MAIN_0_TX_IN_0 |
|
UART0_USART_DMA_OUT_1 |
PDMA1_USART_MAIN_0_RX_IN_0 |
|
|
UART0_USART_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_210 |
|
|
UART0_USART_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_210 |
|
|
UART0_USART_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_210 |
|
|
UART0_USART_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_210 |
|
|
UART0_USART_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_210 |
|
|
UART0_USART_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_210 |
|
|
UART0_USART_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_210 |
|
|
UART1 |
UART1_USART_DMA_OUT_0 |
PDMA1_USART_MAIN_1_TX_IN_0 |
|
UART1_USART_DMA_OUT_1 |
PDMA1_USART_MAIN_1_RX_IN_0 |
|
|
UART1_USART_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_211 |
|
|
UART1_USART_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_211 |
|
|
UART1_USART_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_211 |
|
|
UART1_USART_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_211 |
|
|
UART1_USART_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_211 |
|
|
UART1_USART_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_211 |
|
|
UART1_USART_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_211 |
|
|
UART2 |
UART2_USART_DMA_OUT_0 |
PDMA1_USART_MAIN_2_TX_IN_0 |
|
UART2_USART_DMA_OUT_1 |
PDMA1_USART_MAIN_2_RX_IN_0 |
|
|
UART2_USART_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_212 |
|
|
UART2_USART_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_212 |
|
|
UART2_USART_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_212 |
|
|
UART2_USART_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_212 |
|
|
UART2_USART_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_212 |
|
|
UART2_USART_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_212 |
|
|
UART2_USART_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_212 |
|
|
UART3 |
UART3_USART_DMA_OUT_0 |
PDMA1_USART_MAIN_3_TX_IN_0 |
|
UART3_USART_DMA_OUT_1 |
PDMA1_USART_MAIN_3_RX_IN_0 |
|
|
UART3_USART_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_213 |
|
|
UART3_USART_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_213 |
|
|
UART3_USART_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_213 |
|
|
UART3_USART_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_213 |
|
|
UART3_USART_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_213 |
|
|
UART3_USART_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_213 |
|
|
UART3_USART_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_213 |
|
|
UART4 |
UART4_USART_DMA_OUT_0 |
PDMA1_USART_MAIN_4_TX_IN_0 |
|
UART4_USART_DMA_OUT_1 |
PDMA1_USART_MAIN_4_RX_IN_0 |
|
|
UART4_USART_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_214 |
|
|
UART4_USART_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_214 |
|
|
UART4_USART_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_214 |
|
|
UART4_USART_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_214 |
|
|
UART4_USART_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_214 |
|
|
UART4_USART_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_214 |
|
|
UART4_USART_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_214 |
|
|
UART5 |
UART5_USART_DMA_OUT_0 |
PDMA1_USART_MAIN_5_TX_IN_0 |
|
UART5_USART_DMA_OUT_1 |
PDMA1_USART_MAIN_5_RX_IN_0 |
|
|
UART5_USART_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_215 |
|
|
UART5_USART_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_215 |
|
|
UART5_USART_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_215 |
|
|
UART5_USART_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_215 |
|
|
UART5_USART_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_215 |
|
|
UART5_USART_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_215 |
|
|
UART5_USART_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_215 |
|
|
UART6 |
UART6_USART_DMA_OUT_0 |
PDMA1_USART_MAIN_6_TX_IN_0 |
|
UART6_USART_DMA_OUT_1 |
PDMA1_USART_MAIN_6_RX_IN_0 |
|
|
UART6_USART_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_216 |
|
|
UART6_USART_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_216 |
|
|
UART6_USART_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_216 |
|
|
UART6_USART_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_216 |
|
|
UART6_USART_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_216 |
|
|
UART6_USART_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_216 |
|
|
UART6_USART_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_216 |
|
|
WKUP_UART0 |
WKUP_UART0_CLKSTOP_WAKEUP_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_144 |
|
WKUP_UART0_USART_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_218 |
|
|
WKUP_UART0_USART_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_218 |
|
|
WKUP_UART0_USART_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_219 |
|
|
WKUP_UART0_USART_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_219 |
|
|
WKUP_UART0_USART_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_219 |
|
|
WKUP_UART0_USART_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_219 |
|
|
WKUP_UART0_USART_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_219 |
| OUT Interrupt | Connected To |
|---|---|
|
USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_35 |
|
USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_111 |
|
USB0_HOST_SYSTEM_ERROR_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_32 |
|
USB0_IRQ_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_220 |
|
USB0_IRQ_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_220 |
|
USB0_IRQ_OUT_0 |
R5FSS0_CORE0_INTR_IN_220 |
|
USB0_IRQ_OUT_0 |
R5FSS0_CORE1_INTR_IN_220 |
|
USB0_IRQ_OUT_0 |
R5FSS1_CORE0_INTR_IN_220 |
|
USB0_IRQ_OUT_0 |
R5FSS1_CORE1_INTR_IN_220 |
|
USB0_IRQ_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_220 |
|
USB0_IRQ_OUT_1 |
C7X256V0_CLEC_GIC_SPI_IN_221 |
|
USB0_IRQ_OUT_1 |
C7X256V1_CLEC_GIC_SPI_IN_221 |
|
USB0_IRQ_OUT_1 |
R5FSS0_CORE0_INTR_IN_221 |
|
USB0_IRQ_OUT_1 |
R5FSS0_CORE1_INTR_IN_221 |
|
USB0_IRQ_OUT_1 |
R5FSS1_CORE0_INTR_IN_221 |
|
USB0_IRQ_OUT_1 |
R5FSS1_CORE1_INTR_IN_221 |
|
USB0_IRQ_OUT_1 |
WKUP_R5FSS0_CORE0_INTR_IN_221 |
|
USB0_IRQ_OUT_2 |
C7X256V0_CLEC_GIC_SPI_IN_222 |
|
USB0_IRQ_OUT_2 |
C7X256V1_CLEC_GIC_SPI_IN_222 |
|
USB0_IRQ_OUT_2 |
R5FSS0_CORE0_INTR_IN_222 |
|
USB0_IRQ_OUT_2 |
R5FSS0_CORE1_INTR_IN_222 |
|
USB0_IRQ_OUT_2 |
R5FSS1_CORE0_INTR_IN_222 |
|
USB0_IRQ_OUT_2 |
R5FSS1_CORE1_INTR_IN_222 |
|
USB0_IRQ_OUT_2 |
WKUP_R5FSS0_CORE0_INTR_IN_222 |
|
USB0_IRQ_OUT_3 |
C7X256V0_CLEC_GIC_SPI_IN_223 |
|
USB0_IRQ_OUT_3 |
C7X256V1_CLEC_GIC_SPI_IN_223 |
|
USB0_IRQ_OUT_3 |
R5FSS0_CORE0_INTR_IN_223 |
|
USB0_IRQ_OUT_3 |
R5FSS0_CORE1_INTR_IN_223 |
|
USB0_IRQ_OUT_3 |
R5FSS1_CORE0_INTR_IN_223 |
|
USB0_IRQ_OUT_3 |
R5FSS1_CORE1_INTR_IN_223 |
|
USB0_IRQ_OUT_3 |
WKUP_R5FSS0_CORE0_INTR_IN_223 |
|
USB0_IRQ_OUT_4 |
C7X256V0_CLEC_GIC_SPI_IN_224 |
|
USB0_IRQ_OUT_4 |
C7X256V1_CLEC_GIC_SPI_IN_224 |
|
USB0_IRQ_OUT_4 |
R5FSS0_CORE0_INTR_IN_224 |
|
USB0_IRQ_OUT_4 |
R5FSS0_CORE1_INTR_IN_224 |
|
USB0_IRQ_OUT_4 |
R5FSS1_CORE0_INTR_IN_224 |
|
USB0_IRQ_OUT_4 |
R5FSS1_CORE1_INTR_IN_224 |
|
USB0_IRQ_OUT_4 |
WKUP_R5FSS0_CORE0_INTR_IN_224 |
|
USB0_IRQ_OUT_5 |
C7X256V0_CLEC_GIC_SPI_IN_225 |
|
USB0_IRQ_OUT_5 |
C7X256V1_CLEC_GIC_SPI_IN_225 |
|
USB0_IRQ_OUT_5 |
R5FSS0_CORE0_INTR_IN_225 |
|
USB0_IRQ_OUT_5 |
R5FSS0_CORE1_INTR_IN_225 |
|
USB0_IRQ_OUT_5 |
R5FSS1_CORE0_INTR_IN_225 |
|
USB0_IRQ_OUT_5 |
R5FSS1_CORE1_INTR_IN_225 |
|
USB0_IRQ_OUT_5 |
WKUP_R5FSS0_CORE0_INTR_IN_225 |
|
USB0_IRQ_OUT_6 |
C7X256V0_CLEC_GIC_SPI_IN_226 |
|
USB0_IRQ_OUT_6 |
C7X256V1_CLEC_GIC_SPI_IN_226 |
|
USB0_IRQ_OUT_6 |
R5FSS0_CORE0_INTR_IN_226 |
|
USB0_IRQ_OUT_6 |
R5FSS0_CORE1_INTR_IN_226 |
|
USB0_IRQ_OUT_6 |
R5FSS1_CORE0_INTR_IN_226 |
|
USB0_IRQ_OUT_6 |
R5FSS1_CORE1_INTR_IN_226 |
|
USB0_IRQ_OUT_6 |
WKUP_R5FSS0_CORE0_INTR_IN_226 |
|
USB0_IRQ_OUT_7 |
C7X256V0_CLEC_GIC_SPI_IN_227 |
|
USB0_IRQ_OUT_7 |
C7X256V1_CLEC_GIC_SPI_IN_227 |
|
USB0_IRQ_OUT_7 |
R5FSS0_CORE0_INTR_IN_227 |
|
USB0_IRQ_OUT_7 |
R5FSS0_CORE1_INTR_IN_227 |
|
USB0_IRQ_OUT_7 |
R5FSS1_CORE0_INTR_IN_227 |
|
USB0_IRQ_OUT_7 |
R5FSS1_CORE1_INTR_IN_227 |
|
USB0_IRQ_OUT_7 |
WKUP_R5FSS0_CORE0_INTR_IN_227 |
|
USB0_MISC_LEVEL_OUT_0 |
C7X256V0_CLEC_GIC_SPI_IN_228 |
|
USB0_MISC_LEVEL_OUT_0 |
C7X256V1_CLEC_GIC_SPI_IN_228 |
|
USB0_MISC_LEVEL_OUT_0 |
R5FSS0_CORE0_INTR_IN_228 |
|
USB0_MISC_LEVEL_OUT_0 |
R5FSS0_CORE1_INTR_IN_228 |
|
USB0_MISC_LEVEL_OUT_0 |
R5FSS1_CORE0_INTR_IN_228 |
|
USB0_MISC_LEVEL_OUT_0 |
R5FSS1_CORE1_INTR_IN_228 |
|
USB0_MISC_LEVEL_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_228 |
|
USB0_USB_WAKEUP_CLKSTOP_WAKEUP_OUT_0 |
WKUP_R5FSS0_CORE0_INTR_IN_61 |