SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
In X-Y FIFO mode, the static TR consists of the following information:
| Param | PSIL Addr | Field | Description |
|---|---|---|---|
| Burst | 0x400 | 31 | When set, enables VBUSP burst mode on this channel. See the XY burst description for more information. |
| Acc32 | 0x400 | 30 | When set, enables 32-bit access mode. On a 32-bit PDMA, all accesses will have XCNT=4 to support legacy IP that is not fully VBUSP compliant. This bit is ignored if the PDMA VBUSP port is not 32 bits wide. |
| X | 0x400 | 26:24 | Element size. This field specifies how much data is transferred in each write which is performed by the DMA. This field is encoded as follows: 0 = 8 bits, 1 = 16 bits, 2 = 24 bits, 3 = 32 bits, 4 = 64 bits, and 5-7 = RESERVED |
| Y | 0x400 | 11:0 | Element count. This field specifies how many elements to transfer each time a trigger is received on the channel. |
| Z | 0x401 | 23:0 | Not used |