SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Each channel has a dedicated output FIFO that is filled when the data path writes a sample to the output FIFO. The ASRC keeps tracks of the number of writes to the output FIFO and the number of reads that occur from the VBUS (by a processor, EDMA, or DMA). The outfifo interrupt will fire whenever the amount of available data matches the threshold set in the ASRC_SRCFFCTRL_0[23:16] OUTFIFO_THRESHOLD register field. Status for each FIFO can be checked in the ASRC_OFIRQENSTS status register. Once an OUTFIFO interrupt is fired, next interrupt will be generated only after OUTFIFO_THRESHOLD number of Audio RX Sync pulses has occured for that particular channel.
When the CPU is used to transfer data from ASRC, whenever an outfifo_intr is triggered, SW needs to read the ASRC_OFIRQENSTS status register and needs to determine which channel needs to be serviced. Based on interrupt status register software can trigger DMA to initiate transactions to channels. Data transfer will be in the same manner as described in ASRC Stream Mode Audio Data Read for Channel N with DMA triggered by software instead of outfifo_evt event. After servicing the channel SW needs to clear the interrupt for that particular channel.