SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Hardware Breakpoint 0 Control Register This is the control and status register for hardware breakpoint resources.
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| Instance Name | Physical Address |
|---|---|
| C7X256V0_DEBUG | 0007 3400 0100h |
| C7X256V1_DEBUG | 0007 3800 0100h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | COUNT | COUNT_SUP | RESERVED | CRIT_PROC | CRIT_VMID | ||
| NONE | R/W | R | NONE | R/W | R/W | ||
| 0h | 0h | 1h | 0h | 0h | 0h | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CRIT_DCTXT | RESERVED | CRIT_ADDR | RESERVED | TRIGGERED | AET_EVT | HALT | ENABLE |
| R/W | NONE | R/W | NONE | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:13 | RESERVED | NONE | 0h | Reserved |
| 12 | COUNT | R/W | 0h | When implemented, this 20-bit count field defines the number of times an instruction address match is detected before the trigger is generated Writing n causes this hardware breakpoint resource to generate a trigger upon the [n+1]th occurrence of an instruction address match When set to 0 this hardware breakpoint resource will halt on the first occurrence of an instruction address match Reads return the current value of the supporting occurrence counter |
| 11 | COUNT_SUP | R | 1h | This bit defines whether this hardware breakpoint resource supports occurrence detection via the COUNT bit-field This bit is set by implementation |
| 10 | RESERVED | NONE | 0h | Reserved |
| 9 | CRIT_PROC | R/W | 0h | This bit designates if the processor state match criteria is used to determine a comparison match |
| 8 | CRIT_VMID | R/W | 0h | This bit designates if the VMID match criteria is used to determine a comparison match |
| 7 | CRIT_DCTXT | R/W | 0h | This bit designates if the debug context match criteria is used to determine a comparison match |
| 6 | RESERVED | NONE | 0h | Reserved |
| 5 | CRIT_ADDR | R/W | 0h | This bit designates if the address comparison criteria is used to determine a comparison match |
| 4 | RESERVED | NONE | 0h | Reserved |
| 3 | TRIGGERED | R/W | 0h | This bit indicates that the trigger condition has been met since the last time this bit was cleared |
| 2 | AET_EVT | R/W | 0h | This bit configures the module to generate an AET event when triggered |
| 1 | HALT | R/W | 0h | This bit configures the module to halt the processor when triggered |
| 0 | ENABLE | R/W | 0h | This is the local enable for the hardware breakpoint module |