| MCASP0 |
MCASP0_rec_dma_event_req_0 |
PDMA2_mcasp_main_0_rx_IN_0 |
PDMA2 |
MCASP0 interrupt request |
pulse |
| MCASP0 |
MCASP0_rec_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_267 |
C7X256V0_CLEC |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_rec_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_267 |
C7X256V1_CLEC |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_rec_intr_pend_0 |
R5FSS0_CORE0_intr_IN_120 |
R5FSS0_CORE0 |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_rec_intr_pend_0 |
R5FSS0_CORE1_intr_IN_120 |
R5FSS0_CORE1 |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_rec_intr_pend_0 |
R5FSS1_CORE0_intr_IN_120 |
R5FSS1_CORE0 |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_rec_intr_pend_0 |
R5FSS1_CORE1_intr_IN_120 |
R5FSS1_CORE1 |
MCASP0 interrupt request |
level |
| MCASP0 |
CASP0_xmit_dma_event_req_0 |
DMASS0_INTAGGR_0_intaggr_levi_pend_IN_ |
DMASS0_INTAGGR_0 |
MCASP0 interrupt request |
pulse |
| MCASP0 |
MCASP0_xmit_dma_event_req_0 |
PDMA2_mcasp_main_0_tx_IN_0 |
PDMA2 |
MCASP0 interrupt request |
pulse |
| MCASP0 |
MCASP0_xmit_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_268 |
C7X256V0_CLEC |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_xmit_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_268 |
C7X256V1_CLEC |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_xmit_intr_pend_0 |
R5FSS0_CORE0_intr_IN_121 |
R5FSS0_CORE0 |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_xmit_intr_pend_0 |
R5FSS0_CORE1_intr_IN_121 |
R5FSS0_CORE1 |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_xmit_intr_pend_0 |
R5FSS1_CORE0_intr_IN_121 |
R5FSS1_CORE0 |
MCASP0 interrupt request |
level |
| MCASP0 |
MCASP0_xmit_intr_pend_0 |
R5FSS1_CORE1_intr_IN_121 |
R5FSS1_CORE1 |
MCASP0 interrupt request |
level |
| MCASP1 |
MCASP1_rec_dma_event_req_0 |
PDMA2_mcasp_main_1_rx_IN_0 |
PDMA2 |
MCASP1 interrupt request |
pulse |
| MCASP1 |
MCASP1_rec_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_269 |
C7X256V0_CLEC |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_rec_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_269 |
C7X256V1_CLEC |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_rec_intr_pend_0 |
R5FSS0_CORE0_intr_IN_122 |
R5FSS0_CORE0 |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_rec_intr_pend_0 |
R5FSS0_CORE1_intr_IN_122 |
R5FSS0_CORE1 |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_rec_intr_pend_0 |
R5FSS1_CORE0_intr_IN_122 |
R5FSS1_CORE0 |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_rec_intr_pend_0 |
R5FSS1_CORE1_intr_IN_122 |
R5FSS1_CORE1 |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_xmit_dma_event_req_0 |
DMASS0_INTAGGR_0_intaggr_levi_pend_IN_2 |
DMASS0_INTAGGR_0 |
MCASP1 interrupt request |
pulse |
| MCASP1 |
MCASP1_xmit_dma_event_req_0 |
PDMA2_mcasp_main_1_tx_IN_0 |
PDMA2 |
MCASP1 interrupt request |
pulse |
| MCASP1 |
MCASP1_xmit_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_270 |
C7X256V0_CLEC |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_xmit_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_270 |
C7X256V1_CLEC |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_xmit_intr_pend_0 |
R5FSS0_CORE0_intr_IN_123 |
R5FSS0_CORE0 |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_xmit_intr_pend_0 |
R5FSS0_CORE1_intr_IN_123 |
R5FSS0_CORE1 |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_xmit_intr_pend_0 |
R5FSS1_CORE0_intr_IN_123 |
R5FSS1_CORE0 |
MCASP1 interrupt request |
level |
| MCASP1 |
MCASP1_xmit_intr_pend_0 |
R5FSS1_CORE1_intr_IN_123 |
R5FSS1_CORE1 |
MCASP1 interrupt request |
level |
| MCASP2 |
MCASP2_rec_dma_event_req_0 |
PDMA2_mcasp_main_2_rx_IN_0 |
PDMA2 |
MCASP2 interrupt request |
pulse |
| MCASP2 |
MCASP2_rec_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_271 |
C7X256V0_CLEC |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_rec_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_271 |
C7X256V1_CLEC |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_rec_intr_pend_0 |
R5FSS0_CORE0_intr_IN_124 |
R5FSS0_CORE0 |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_rec_intr_pend_0 |
R5FSS0_CORE1_intr_IN_124 |
R5FSS0_CORE1 |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_rec_intr_pend_0 |
R5FSS1_CORE0_intr_IN_124 |
R5FSS1_CORE0 |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_rec_intr_pend_0 |
R5FSS1_CORE1_intr_IN_124 |
R5FSS1_CORE1 |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_xmit_dma_event_req_0 |
DMASS0_INTAGGR_0_intaggr_levi_pend_IN_3 |
DMASS0_INTAGGR_0 |
MCASP2 interrupt request |
pulse |
| MCASP2 |
MCASP2_xmit_dma_event_req_0 |
PDMA2_mcasp_main_2_tx_IN_0 |
PDMA2 |
MCASP2 interrupt request |
pulse |
| MCASP2 |
MCASP2_xmit_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_272 |
C7X256V0_CLEC |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_xmit_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_272 |
C7X256V1_CLEC |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_xmit_intr_pend_0 |
R5FSS0_CORE0_intr_IN_125 |
R5FSS0_CORE0 |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_xmit_intr_pend_0 |
R5FSS0_CORE1_intr_IN_125 |
R5FSS0_CORE1 |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_xmit_intr_pend_0 |
R5FSS1_CORE0_intr_IN_125 |
R5FSS1_CORE0 |
MCASP2 interrupt request |
level |
| MCASP2 |
MCASP2_xmit_intr_pend_0 |
R5FSS1_CORE1_intr_IN_125 |
R5FSS1_CORE1 |
MCASP2 interrupt request |
level |
| MCASP3 |
MCASP3_rec_dma_event_req_0 |
PDMA3_mcasp_main_3_rx_IN_0 |
PDMA3 |
MCASP3 interrupt request |
pulse |
| MCASP3 |
MCASP3_rec_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_273 |
C7X256V0_CLEC |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_rec_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_273 |
C7X256V1_CLEC |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_rec_intr_pend_0 |
R5FSS0_CORE0_intr_IN_126 |
R5FSS0_CORE0 |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_rec_intr_pend_0 |
R5FSS0_CORE1_intr_IN_126 |
R5FSS0_CORE1 |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_rec_intr_pend_0 |
R5FSS1_CORE0_intr_IN_126 |
R5FSS1_CORE0 |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_rec_intr_pend_0 |
R5FSS1_CORE1_intr_IN_126 |
R5FSS1_CORE1 |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_xmit_dma_event_req_0 |
DMASS0_INTAGGR_0_intaggr_levi_pend_IN_5 |
DMASS0_INTAGGR_0 |
MCASP3 interrupt request |
pulse |
| MCASP3 |
MCASP3_xmit_dma_event_req_0 |
PDMA3_mcasp_main_3_tx_IN_0 |
PDMA3 |
MCASP3 interrupt request |
pulse |
| MCASP3 |
MCASP3_xmit_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_274 |
C7X256V0_CLEC |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_xmit_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_274 |
C7X256V1_CLEC |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_xmit_intr_pend_0 |
R5FSS0_CORE0_intr_IN_127 |
R5FSS0_CORE0 |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_xmit_intr_pend_0 |
R5FSS0_CORE1_intr_IN_127 |
R5FSS0_CORE1 |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_xmit_intr_pend_0 |
R5FSS1_CORE0_intr_IN_127 |
R5FSS1_CORE0 |
MCASP3 interrupt request |
level |
| MCASP3 |
MCASP3_xmit_intr_pend_0 |
R5FSS1_CORE1_intr_IN_127 |
R5FSS1_CORE1 |
MCASP3 interrupt request |
level |
| MCASP4 |
MCASP4_rec_dma_event_req_0 |
PDMA3_mcasp_main_4_rx_IN_0 |
PDMA3 |
MCASP4 interrupt request |
pulse |
| MCASP4 |
MCASP4_rec_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_275 |
C7X256V0_CLEC |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_rec_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_275 |
C7X256V1_CLEC |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_rec_intr_pend_0 |
R5FSS0_CORE0_intr_IN_130 |
R5FSS0_CORE0 |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_rec_intr_pend_0 |
R5FSS0_CORE1_intr_IN_130 |
R5FSS0_CORE1 |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_rec_intr_pend_0 |
R5FSS1_CORE0_intr_IN_130 |
R5FSS1_CORE0 |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_rec_intr_pend_0 |
R5FSS1_CORE1_intr_IN_130 |
R5FSS1_CORE1 |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_xmit_dma_event_req_0 |
DMASS0_INTAGGR_0_intaggr_levi_pend_IN_5 |
DMASS0_INTAGGR_0 |
MCASP4 interrupt request |
pulse |
| MCASP4 |
MCASP4_xmit_dma_event_req_0 |
PDMA3_mcasp_main_4_tx_IN_0 |
PDMA3 |
MCASP4 interrupt request |
pulse |
| MCASP4 |
MCASP4_xmit_intr_pend_0 |
C7X256V0_CLEC_gic_spi_IN_276 |
C7X256V0_CLEC |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_xmit_intr_pend_0 |
C7X256V1_CLEC_gic_spi_IN_276 |
C7X256V1_CLEC |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_xmit_intr_pend_0 |
R5FSS0_CORE0_intr_IN_131 |
R5FSS0_CORE0 |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_xmit_intr_pend_0 |
R5FSS0_CORE1_intr_IN_131 |
R5FSS0_CORE1 |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_xmit_intr_pend_0 |
R5FSS1_CORE0_intr_IN_131 |
R5FSS1_CORE0 |
MCASP4 interrupt request |
level |
| MCASP4 |
MCASP4_xmit_intr_pend_0 |
R5FSS1_CORE1_intr_IN_131 |
R5FSS1_CORE1 |
MCASP4 interrupt request |
level |