SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Input side Audio Sample Clock can be selected through the mux select bits described in Table 12-5. The Output Side Audio Sample Clock can be selected through the mux bits described in Table 12-6.
| Mux Select (ASRC[0:1]_RXSYNC[0:4]_SEL_SYNC_SEL) | SYNC Source |
|---|---|
| 0 | MCASP0_AFSR Pin Input |
| 1 | MCASP1_AFSR Pin Input |
| 2 | MCASP2_AFSR Pin Input |
| 3 | MCASP3_AFSR Pin Input |
| 4 | MCASP4_AFSR Pin Input |
| 8 | MCASP0 AFSX Pin Input |
| 9 | MCASP1 AFSX Pin Input |
| 10 | MCASP2 AFSX Pin Input |
| 11 | MCASP3 AFSX Pin Input |
| 12 | MCASP4 AFSX Pin Input |
| 16 | AUDIO_EXT_REFCLK0_IN |
| 17 | AUDIO_EXT_REFCLK1_IN |
| 18 | AUDIO_EXT_REFCLK2_IN |
| 20 | ADC0_CLK |
| 21 | MLB_IO_CLK |
| 22 | DIV_PLL4_HSDIV3_CLKOUT |
| 24 | MCU_EXT_REFCLK0 |
| 25 | EXT_REFCLK1 |
| 26 | CPSW_3GUSS_CPTS_GENF0 |
| 27 | CPSW_3GUSS_CPTS_GENF1 |
| Mux Select (ASRC[0:1]_TXSYNC[0:4]_SEL_SYNC_SEL) | SYNC Source |
|---|---|
| 0 | MCASP0_AFSR Pin Input |
| 1 | MCASP1_AFSR Pin Input |
| 2 | MCASP2_AFSR Pin Input |
| 3 | MCASP3_AFSR Pin Input |
| 4 | MCASP4_AFSR Pin Input |
| 8 | MCASP0 AFSX Pin Input |
| 9 | MCASP1 AFSX Pin Input |
| 10 | MCASP2 AFSX Pin Input |
| 11 | MCASP3 AFSX Pin Input |
| 12 | MCASP4 AFSX Pin Input |
| 16 | AUDIO_EXT_REFCLK0_IN |
| 17 | AUDIO_EXT_REFCLK1_IN |
| 18 | AUDIO_EXT_REFCLK2_IN |
| 20 | ADC0_CLK |
| 21 | MLB_IO_CLK |
| 22 | DIV_PLL4_HSDIV3_CLKOUT |
| 24 | MCU_EXT_REFCLK0 |
| 25 | EXT_REFCLK1 |
| 26 | CPSW_3GUSS_CPTS_GENF0 |
| 27 | CPSW_3GUSS_CPTS_GENF1 |