SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Event Trigger Flag Register
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| Instance Name | Physical Address |
|---|---|
| EPWM0 | 2300 0036h |
| EPWM1 | 2301 0036h |
| EPWM2 | 2302 0036h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED1 | INT | ||||||
| R | R | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 15:1 | RESERVED1 | R | 0h | Reserved |
| 0 | INT | R | 0h | Latched ePWM Interrupt [EPWMx_INT] Status Flag 0h Indicates no event occurred.
1h Indicates that an EPWMx interrupt
(EWPMx_INT) was generated. No further
interrupts will be generated until the flag
bit is cleared. Up to one interrupt can be
pending while the EPWM_ETFLG[0] INT bit is
still set. If an interrupt is pending, it
will not be generated until after the
EPWM_ETFLG[0] INT bit is cleared. |