SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global Debug Endpoint Information Register 1 This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration, then the default values readout is X (Undefined). Bit Bash test should not be done on this debug register.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C17Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| EPDEBUG | |||||||
| R | |||||||
| 800000h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| EPDEBUG | |||||||
| R | |||||||
| 800000h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EPDEBUG | |||||||
| R | |||||||
| 800000h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| EPDEBUG | |||||||
| R | |||||||
| 800000h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | EPDEBUG | R | 800000h | Endpoint Debug Information, bits[63:32] Reset Source: rst_mod_g_rst_n |