SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The IIR is a read-only register, which provides the source of the interrupt in a prioritized manner.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0008h |
| UART1 | 0281 0008h |
| UART2 | 0282 0008h |
| UART3 | 0283 0008h |
| UART4 | 0284 0008h |
| UART5 | 0285 0008h |
| UART6 | 0286 0008h |
| WKUP_UART0 | 2B30 0008h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TX_STATUS_IT | RESERVED | RX_OE_IT | RX_STOP_IT | THR_IT | RHR_IT | |
| NONE | R | NONE | R | R | R | R | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:6 | RESERVED | NONE | 0h | Reserved |
| 5 | TX_STATUS_IT | R | 0h | 0 TX status interrupt inactive 1 TX status interrupt active |
| 4 | RESERVED | NONE | 0h | Reserved |
| 3 | RX_OE_IT | R | 0h | 0 RX overrun interrupt inactive 1 RX overrun interrupt active |
| 2 | RX_STOP_IT | R | 0h | 0 Receive stop interrupt inactive 1 Receive stop interrupt active |
| 1 | THR_IT | R | 0h | 0 THR interrupt inactive 1 THR interrupt active |
| 0 | RHR_IT | R | 0h | 0 RHR interrupt inactive 1 RHR interrupt active |