SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The sources for BWS and AWS inputs are defined by internal muxing from multiple reference signals.
BWS and AWS are logic inputs, not clocks, to the ATL module. ATL performs an edge detection on these signals. To minimize jitter in HD Radio clocking implementation, ATL_PCLK must be higher than 100 MHz. When ATL is used for HD Radio applications, the measuring circuit is connected to the word select signal from Audio IIS output (AWS) and Baseband IIS input (BWS). The (ATL0_BWSMUX, ATL1_BWSMUX, ATL2_BWSMUX, and ATL3_BWSMUX) and (ATL0_AWSMUX, ATL1_AWSMUX, ATL2_AWSMUX, and ATL3_AWSMUX) registers select which inputs are used as the ATL BWS and AWS inputs.