SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This section describes the HyperBus external connections (environment).
Figure 12-189 shows the HyperBus connected to HyperRAM or HyperFlash.

HyperBus I/O Signals describes the HyperBus I/O signals.
| Module Pin | Device Level Signal(1) | I/O(2) | Description | Module Pin Reset Value |
|---|---|---|---|---|
| MCU_FSS0_HPB0 | ||||
| CK | HYPERBUS0_CK | O | HyperBus Clock Output (differential) | 0x0 |
| CKn | HYPERBUS0_CKn | O | HyperBus Inverted Clock Output (differential) | 0x1 |
| RWDS | HYPERBUS0_RWDS | I/O/HiZ | HyperBus Read/Write Data Strobe | 0x1 |
| DQ[7:0] | HYPERBUS0_DQ[7:0] | I/O/HiZ | HyperBus Data | 0x0 |
| CSn0 | HYPERBUS0_CSn0 | O | HyperBus Chip Select 0 | 0x1 |
| CSn1 | HYPERBUS0_CSn1 | O | HyperBus Chip Select 1 | 0x1 |
| RESETn | HYPERBUS0_RESETn | O | HyperBus Reset Output | 0x1 |
| RESETOn | HYPERBUS0_RESETOn | I | Reset State Indicator (output from HyperBus memory) |
0x1 |
| INTn | HYPERBUS0_INTn | I | Memory Interrupt (output from HyperBus memory) |
0x1 |
| WPn(3) | HYPERBUS0_WPn | O | HyperBus Write Protect (output to HyperBus memory) |
0x1 |
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.