SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The SMS will issue this reset upon a security error.
When this reset is enabled in MAIN domain, it causes a MAIN domain warm reset.
This is a synchronous reset type (needs to complete reset isolation sequence).
This reset behavior is same as the RESETz_REQ reset signal (RESET_REQz HW Pin).
When Top Level domain is configured to operate independently, Top Level domain reset isolation sequence is completed before propagating the RESETz to main domain.
Top Level IOs are not affected.
When MCU domain is not configured as independent then, this reset will also warm reset MCU domain.
This is a MAIN domain warm reset request. First, the reset isolation sequence is applied and then the reset is propagated.
All modules in MAIN domain are reset except for CTRLMMR register bits which are reset only on PORz.
IOs are not affected.
All processor cores are reset
Reason for this reset is captured in CTRLMMR reset source status register MCU CTRLMMR, and the reset isolation sequence status in the main_iso_done bit. After reset is de-asserted, device will boot-up. During device boot-up, R5FSS (secondary boot loader) will read the reset status and reconfigure the domains and processor accordingly.