SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global SoC Bus Configuration Register 0 This register configures system bus DMA options for the initiator bus, which may be configured as AHB, AXI, or Native. Options include burst length and cache type (bufferable/posted, cacheable/snoop, and so on). The application can program this register upon power-on, or a change in mode of operation after the DMA engine is halted. xHCI Register Power-On Value: If you are using a standard xHCI host driver, make sure to set the register's power-on value during coreConsultant configuration (DWC_USB3_GSBUSCFG0_INIT parameter) because the standard xHCI driver does not access this register. For more details on this register, refer to the following sections: - "Usage of Global SoC Bus Configuration Register 0 (GSBUSCFG0)" section in the Programming Guide - "System Bus Interface" section in the Databook
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C100h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DATRDREQINFO | DESRDREQINFO | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DATWRREQINFO | DESWRREQINFO | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_15_12 | DATBIGEND | DESBIGEND | RESERVED_9_8 | ||||
| R | R/W | R/W | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INCR256BRSTENA | INCR128BRSTENA | INCR64BRSTENA | INCR32BRSTENA | INCR16BRSTENA | INCR8BRSTENA | INCR4BRSTENA | INCRBRSTENA |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 1h | 1h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | DATRDREQINFO | R/W | 0h | DATRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Read [DatRdReqInfo] Input to BUS-GM. Reset Source: rst_mod_g_rst_n |
| 27:24 | DESRDREQINFO | R/W | 0h | DESRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read [DesRdReqInfo]. Input to BUS-GM. Reset Source: rst_mod_g_rst_n |
| 23:20 | DATWRREQINFO | R/W | 0h | DATWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Write [DatWrReqInfo]. Input to BUS-GM. Reset Source: rst_mod_g_rst_n |
| 19:16 | DESWRREQINFO | R/W | 0h | DESWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write [DesWrReqInfo] Input to BUS-GM. Reset Source: rst_mod_g_rst_n |
| 15:12 | RESERVED_15_12 | R | 0h | Reserved for future use |
| 11 | DATBIGEND | R/W | 0h | Data Access is Big Endian This bit controls the endian mode for data accesses. - Little-endian [default]. - Big-endian. In big-endian mode, DMA access [both read and write] for packet data a Byte Invariant Big-Endian mode [see "Little-Endian and Big-Endian" section in the User Guide]. Note: Since AXI requires byte invariant endianness, setting DescBigend and DatBigEnd to one causes an address invariant transform to be applied, which is not appropriate. See section 9.3 and 9.4 of the AMBA AXI Specification. Hence for an AXI initiator [DWC_USB3_MBUS_TYPE=1], this bit must be set to zero. Reset Source: rst_mod_g_rst_n |
| 10 | DESBIGEND | R/W | 0h | Descriptor Access is Big Endian This bit controls the endian mode for descriptor accesses. - Little-endian [default] - Big-endian In big-endian mode, DMA access [both read and write] for descriptors uses a Byte Invariant Big-Endian mode [see "Little-Endian and Big-Endian" section in the User Guide. Data is considered as 'embedded data' in the descriptors in the following cases: - Device mode: The buffer pointer of a Setup TRB points to the Setup TRB itself. - Host mode: The Immediate Data [IDT] bit in a Transfer TRB is set to 1. In device mode, if the system uses different endian modes for descriptor and data, software must not use 'embedded' data. In host mode, if the system uses different endian modes for data and descriptors, the controller treats 'embedded data' as descriptor [not as data] in terms of endian mode handling. If this is not the expectation of the system, the software must manipulate the 'embedded data' accordingly. Note: Since AXI requires byte invariant endianness, setting DescBigend and DatBigEnd to one causes an address invariant transform to be applied, which is not appropriate. See section 9.3 and 9.4 of the AMBA AXI Specification. Hence for an AXI initiator [DWC_USB3_MBUS_TYPE=1], this bit must be set to zero. Reset Source: rst_mod_g_rst_n |
| 9:8 | RESERVED_9_8 | R | 0h | Reserved |
| 7 | INCR256BRSTENA | R/W | 0h | INCR256 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI initiator uses INCR to do the 256-beat burst. Reset Source: rst_mod_g_rst_n |
| 6 | INCR128BRSTENA | R/W | 0h | INCR128 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI initiator uses INCR to do the 128-beat burst. Reset Source: rst_mod_g_rst_n |
| 5 | INCR64BRSTENA | R/W | 0h | INCR64 Burst Type Enable - Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI initiator uses INCR to do the 64-beat burst. Reset Source: rst_mod_g_rst_n |
| 4 | INCR32BRSTENA | R/W | 0h | INCR32 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to 1, the AHB/AXI initiator uses INCR to do the 32-beat burst. Reset Source: rst_mod_g_rst_n |
| 3 | INCR16BRSTENA | R/W | 0h | INCR16 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to '1', the AHB/AXI initiator uses INCR to do the 16-beat burst. Reset Source: rst_mod_g_rst_n |
| 2 | INCR8BRSTENA | R/W | 1h | INCR8 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration, if software set this bit to "1", the AHB/AXI initiator uses INCR to do the 8-beat burst. Reset Source: rst_mod_g_rst_n |
| 1 | INCR4BRSTENA | R/W | 1h | INCR4 Burst Type Enable Input to BUS-GM. For the AXI configuration, when this bit is enabled the controller is allowed to do bursts of beat length 1, 2, and 4. It is highly recommended that this bit is enabled to prevent descriptor reads and writes from being broken up into separate transfers. Reset Source: rst_mod_g_rst_n |
| 0 | INCRBRSTENA | R/W | 0h | Undefined Length INCR Burst Type Enable [INCRBrstEna] Input to BUS-GM. This bit determines the set of burst lengths the initiator interface uses. It works in conjunction with the GSBUSCFG0[7:1] enables [INCR256/128/64/32/16/8/4]. 0: INCRX burst mode HBURST [for AHB configurations] and ARLEN/AWLEN [for AXI configurations] do not use INCR except in case of non-aligned burst transfers. In the case of address-aligned transfers, they use only the following burst lengths: - 1 - 2, 4 [if GSBUSCFG0.INCR4BrstEna = 1] - 8 [if GSBUSCFG0.INCR8BrstEna = 1] - 16 [if GSBUSCFG0.INCR16BrstEna = 1] - 32 [if GSBUSCFG0.INCR32BrstEna = 1] - 64 [if GSBUSCFG0.INCR64BrstEna = 1] - 128 [if GSBUSCFG0.INCR128BrstEna = 1] - 256 [if GSBUSCFG0.INCR256BrstEna = 1] Note: - In case of non-address-aligned transfers, INCR may get generated at the beginning and end of the transfers to align the address boundaries, even though INCR is disabled. - In AHB mode, if INCRX burst mode is enabled, but none of the supported INCRx bursts bits are enabled, then the controller will perform [undefined length] INCR bursts. 1: INCR [undefined length] burst mode - AHB configurations: HBURST uses SINGLE or INCR of any length with handling 1KB boundary breakup. - AXI configurations: ARLEN/AWLEN uses any length less than or equal to the largest-enabled burst length of INCR32/64/128/256. For cache line-aligned applications, this bit is typically set to 0 to ensure that the initiator interface uses only power-of-2 burst lengths [as enabled via GSBUSCFG0[7:0]]. Reset Source: rst_mod_g_rst_n |