SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Determines the length of the timing window during which a monitored wakeup event will generate an IPOR. This ensures wakeup events occurring soon after PMIC_EN deactivation but before IORET state entry are recognized. After this window has expired, the external PMIC is expected to generate a POR based on PMIC_EN activation. The ImmediateWakeup Timeout window is disabled (no IPOR generated) if the wake_timeout_dis in WAKE_EVT_MON_CTRL is 1.
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4301 8368h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IMMED_WAKE_TIMEOUT_TIMEOUT_LENGTH | |||||||
| R/W | |||||||
| EAh | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IMMED_WAKE_TIMEOUT_TIMEOUT_LENGTH | |||||||
| R/W | |||||||
| EAh | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED | NONE | 0h | Reserved |
| 15:0 | IMMED_WAKE_TIMEOUT_TIMEOUT_LENGTH | R/W | EAh | Specifies the number of HFOSC0 clock cycles during which wake monitoring logic will issue an internal POR. This timeout value must exceed the PMIC glitch filtering window for its PMIC_EN input. (Default value is 9 s at 26 MHz HFOSC0) Reset Source: mod_por_rst_n |