SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Link Datapath Delay Register - Link Layer Timer Register for P3CPM/P4 Residency. - This register is common for all SS ports.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 D028h + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_22_31 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_22_31 | P3CPMP4_RESIDENCY | ||||||
| R/W | R/W | ||||||
| 0h | 3h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| P3CPMP4_RESIDENCY | RESERVED_0_9 | ||||||
| R/W | R/W | ||||||
| 3h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_0_9 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:22 | RESERVED_22_31 | R/W | 0h | Reserved |
| 21:10 | P3CPMP4_RESIDENCY | R/W | 3h | p3cpmp4 residency timer value. Minimum number of suspend_clk periods that the controller needs to stay in P3.CPM or P4 before exiting P3.CPM or P4. This field is used only for Synopsys PHY. Reset Source: rst_mod_g_rst_n |
| 9:0 | RESERVED_0_9 | R/W | 0h | Reserved |