SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The IRQ_ENABLE_SET register allows the interrupt sources associated with each bit in this register to be manually enabled when writing a 1 to a specific bit. This register corresponds to fsas_ecc_intr_err_pend (level) and fsas_ecc_intr_err_req (pulse) interrupt outputs. Write 0: No action Write 1: Enable event Read 0: Event is disabled Read 1: Event is enabled
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| Instance Name | Physical Address |
|---|---|
| FSS0 | 0FC1 001Ch + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DP_RET_ERROR | DP_CMD_ERROR | ECC_WRITE_NONALIGN | ECC_ERROR_2BIT | ECC_ERROR_1BIT | ||
| NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:5 | RESERVED | NONE | 0h | Reserved |
| 4 | DP_RET_ERROR | R/W1TS | 0h | Safety double pumping read return error Reset Source: vbus_mod_g_rst_n |
| 3 | DP_CMD_ERROR | R/W1TS | 0h | Safety double pumping command error Reset Source: vbus_mod_g_rst_n |
| 2 | ECC_WRITE_NONALIGN | R/W1TS | 0h | Write is not aligned to 32B boundary or not a multiple of 32B Reset Source: vbus_mod_g_rst_n |
| 1 | ECC_ERROR_2BIT | R/W1TS | 0h | ECC error on 2 bits. Not correctable Reset Source: vbus_mod_g_rst_n |
| 0 | ECC_ERROR_1BIT | R/W1TS | 0h | ECC error on 1 bits. corrected Reset Source: vbus_mod_g_rst_n |