SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The selection of the working mode is done with the MCSPI_CH(i)CONF register.
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Set receive mode for the channel. | MCSPI_CH(i)CONF[13-12] TRM | 0x1 |
| Configure SPI clock polarity/phase, clock divider, word length, and others for the channel. | MCSPI_CH(i)CONF | 0x- |
| Reset the status bits. | MCSPI_IRQSTATUS | 0x0 |
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Set transmit mode for the channel. | MCSPI_CH(i)CONF[13-12] TRM | 0x2 |
| Configure SPI clock polarity/phase, clock divider, word length, and others for the channel. | MCSPI_CH(i)CONF | 0x- |
| Reset the status bits. | MCSPI_IRQSTATUS | 0x0 |
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Set transmit and receive mode for the channel. | MCSPI_CH(i)CONF[13-12] TRM | 0x0 |
| Configure SPI clock polarity/phase, clock divider, word length, and others for the channel. | MCSPI_CH(i)CONF | 0x- |
| Reset the status bits. | MCSPI_IRQSTATUS | 0x0 |