SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global Debug LTSSM Register In multi-port host configuration, the port-number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: - GDBGLTSSM register is not applicable for USB 2.0-only mode. - Bit Bash test should not be done on this debug register.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C164h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_31 | RXELECIDLE | X3_XS_SWAPPING | X3_DS_HOST_SHUTDOWN | PRTDIRECTION | LTDBTIMEOUT | LTDBLINKSTATE | |
| R | R | R | R | R | R | R | |
| 0h | 1h | 0h | 0h | 0h | 0h | 4h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| LTDBLINKSTATE | LTDBSUBSTATE | ELASTICBUFFERMODE | TXELECLDLE | ||||
| R | R | R | R | ||||
| 4h | 0h | 0h | 1h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RXPOLARITY | TXDETRXLOOPBACK | LTDBPHYCMDSTATE | POWERDOWN | RXEQTRAIN | |||
| R | R | R | R | R | |||
| 0h | 0h | 0h | 2h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TXDEEMPHASIS | LTDBCLKSTATE | TXSWING | RXTERMINATION | TXONESZEROS | |||
| R | R | R | R | R | |||
| 1h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED_31_31 | R | 0h | Reserved |
| 30 | RXELECIDLE | R | 1h | RxElecidle For description of RxElecIdle, see table 5-4, "Status Interface Signals" of the PIPE3 Specification. Reset Source: rst_mod_g_rst_n |
| 29 | X3_XS_SWAPPING | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 28 | X3_DS_HOST_SHUTDOWN | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 27 | PRTDIRECTION | R | 0h | Reserved Reset Source: rst_mod_g_rst_n |
| 26 | LTDBTIMEOUT | R | 0h | LTDB Timeout [LTDBTimeout] Reset Source: rst_mod_g_rst_n |
| 25:22 | LTDBLINKSTATE | R | 4h | LTDB Link State [LTDBLinkState] Reset Source: rst_mod_g_rst_n |
| 21:18 | LTDBSUBSTATE | R | 0h | LTDB Sub-State [LTDBSubState] Reset Source: rst_mod_g_rst_n |
| 17 | ELASTICBUFFERMODE | R | 0h | Elastic Buffer Mode [ElasticBufferMode] For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 16 | TXELECLDLE | R | 1h | Tx Elec Idle [TxElecIdle] For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 15 | RXPOLARITY | R | 0h | Rx Polarity [RxPolarity] For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 14 | TXDETRXLOOPBACK | R | 0h | Tx Detect Rx/Loopback [TxDetRxLoopback] For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 13:11 | LTDBPHYCMDSTATE | R | 0h | LTSSM PHY command State [LTDBPhyCmdState] - 000: PHY_IDLE [PHY command state is in IDLE. No PHY request pending] - 001: PHY_DET [Request to start Receiver detection] - 010: PHY_DET_3 [Wait for Phy_Status [Receiver detection]] - 011: PHY_PWR_DLY [Delay Pipe3_PowerDown P0 -> P1/P2/P3 request] - 100: PHY_PWR_A [Delay for internal logic] - 101: PHY_PWR_B [Wait for Phy_Status[Power state change request]] Reset Source: rst_mod_g_rst_n |
| 10:9 | POWERDOWN | R | 2h | POWERDOWN [PowerDown] For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 8 | RXEQTRAIN | R | 0h | RxEq Train For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 7:6 | TXDEEMPHASIS | R | 1h | TXDEEMPHASIS [TxDeemphasis] For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 5:3 | LTDBCLKSTATE | R | 0h | LTSSM Clock State [LTDBClkState] In multi-port host configuration, the port number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: GDBGLTSSM register is not applicable for USB 2.0-only mode. - 000: CLK_NORM [PHY is in non-P3 state and PCLK is running] - 001: CLK_TO_P3 [P3 entry request to PHY]. - 010: CLK_WAIT1 [Wait for Phy_Status [P3 request]]. - 011: CLK_P3 [PHY is in P3 and PCLK is not running]. - 100: CLK_TO_P0 [P3 exit request to PHY]. - 101: CLK_WAIT2 [Wait for Phy_Status [P3 exit request]] Reset Source: rst_mod_g_rst_n |
| 2 | TXSWING | R | 0h | Tx Swing [TxSwing] For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |
| 1 | RXTERMINATION | R | 0h | Rx Termination [RxTermination] For details on DWC_USB3_PIPE_RXTERM_RESET_VAL, refer to <workspace>/src/DWC_usb3_params.v Reset Source: rst_mod_g_rst_n |
| 0 | TXONESZEROS | R | 0h | Tx Ones/Zeros [TxOnesZeros] For field definition, refer to Table 5-3 of the PIPE3 specification. Reset Source: rst_mod_g_rst_n |