The FSS provides access to external Flash and RAM devices. It supports XIP (Execute-in-Place) and BC (Block Copy) operations. The FSS consists of one OSPIs and one HyperBus interface.
Figure 12-182 shows the FSS block diagram
FSS Blocks:
- CBASS: The CBASS interconnect allows FSS to communicate with the device modules and subsystems.
- Data Interface (FSS): It is 64-bit data/32-bit address multi issue data interface with coherent in-band bypass. It provides accessibility to either the OSPI or HyperBus interface.
- Config Interface: It is used for configuration of the memory mapped registers within the FSS.
- For more information about Interface Clock, Resets, and Interrupts, see Flash Subsystem (FSS) in Module Integration
- Memory Mapped Registers: This block includes the FSS registers. The configuration of these registers defines which FSS features are used. For more information, see Memory Interface Registers.
- MUX: The Muxing (MUX) block is used as a software controlled switch in the interface. It defines which interface to be used (OSPI or HyperBus interface). The MUX block can switch only when the traffic is idle. The software has responsibility to cause the traffic to be stopped.
- DF: The Dynamic Fragmenter (DF) module is responsible for fragmenting write data to the flash region so that all writes to the flash region are done in 16-bits chunks (a requirement for HyperFlash). It passes all other transaction through unaffected.
- FSS Interfaces:
- OSPI: Octal Serial Peripheral Interface. For more information, see OSPI I/O Signals
- HPB: HyperBus interface. For more information, see HyperBus I/O Signals