| MAIN_CTRL_MMR0 |
MAIN_CTRL_MMR0_IPC_SET0_ipc_set_ipcfg_0 |
C7X256V0_CLEC_soc_events_in_IN_5 |
C7X256V0_CLEC |
MAIN_CTRL_MMR0 interrupt request |
level |
| MAIN_CTRL_MMR0_IPC_SET16_ipc_set_ipcfg_0 |
R5FSS0_CORE0_intr_IN_0 |
R5FSS0_CORE0 |
MAIN_CTRL_MMR0 interrupt request |
level |
| MAIN_CTRL_MMR0_IPC_SET17_ipc_set_ipcfg_0 |
R5FSS0_CORE1_intr_IN_0 |
R5FSS0_CORE1 |
MAIN_CTRL_MMR0 interrupt request |
level |
| MAIN_CTRL_MMR0_IPC_SET18_ipc_set_ipcfg_0 |
R5FSS1_CORE0_intr_IN_0 |
R5FSS1_CORE0 |
MAIN_CTRL_MMR0 interrupt request |
level |
| MAIN_CTRL_MMR0_IPC_SET19_ipc_set_ipcfg_0 |
R5FSS1_CORE1_intr_IN_0 |
R5FSS1_CORE1 |
MAIN_CTRL_MMR0 interrupt request |
level |
| MAIN_CTRL_MMR0_IPC_SET1_ipc_set_ipcfg_0 |
C7X256V1_CLEC_soc_events_in_IN_5 |
C7X256V1_CLEC |
MAIN_CTRL_MMR0 interrupt request |
level |
| MAIN_CTRL_MMR0_access_err_0 |
C7X256V0_CLEC_gic_spi_IN_129 |
C7X256V0_CLEC |
MAIN_CTRL_MMR0 interrupt request |
level |
| C7X256V1_CLEC_gic_spi_IN_129 |
C7X256V1_CLEC |
MAIN_CTRL_MMR0 interrupt request |
level |
| R5FSS0_CORE0_intr_IN_128 |
R5FSS0_CORE0 |
MAIN_CTRL_MMR0 interrupt request |
level |
| R5FSS0_CORE1_intr_IN_128 |
R5FSS0_CORE1 |
MAIN_CTRL_MMR0 interrupt request |
level |
| R5FSS1_CORE0_intr_IN_128 |
R5FSS1_CORE0 |
MAIN_CTRL_MMR0 interrupt request |
level |
| R5FSS1_CORE1_intr_IN_128 |
R5FSS1_CORE1 |
MAIN_CTRL_MMR0 interrupt request |
level |
| WKUP_R5FSS0_CORE0_intr_IN_128 |
WKUP_R5FSS0_CORE0 |
MAIN_CTRL_MMR0 interrupt request |
level |
| MCU_CTRL_MMR0 |
MCU_CTRL_MMR0_IPC_SET0_ipc_set_ipcfg_0 |
WKUP_R5FSS0_CORE0_intr_IN_0 |
WKUP_R5FSS0_CORE0 |
MCU_CTRL_MMR0 interrupt request |
level |
| MCU_CTRL_MMR0_access_err_0 |
C7X256V0_CLEC_gic_spi_IN_129 |
C7X256V0_CLEC |
MCU_CTRL_MMR0 interrupt request |
level |
| C7X256V1_CLEC_gic_spi_IN_129 |
C7X256V1_CLEC |
MCU_CTRL_MMR0 interrupt request |
level |
| R5FSS0_CORE0_intr_IN_128 |
R5FSS0_CORE0 |
MCU_CTRL_MMR0 interrupt request |
level |
| R5FSS0_CORE1_intr_IN_128 |
R5FSS0_CORE1 |
MCU_CTRL_MMR0 interrupt request |
level |
| R5FSS1_CORE0_intr_IN_128 |
R5FSS1_CORE0 |
MCU_CTRL_MMR0 interrupt request |
level |
| R5FSS1_CORE1_intr_IN_128 |
R5FSS1_CORE1 |
MCU_CTRL_MMR0 interrupt request |
level |
| WKUP_R5FSS0_CORE0_intr_IN_128 |
WKUP_R5FSS0_CORE0 |
MCU_CTRL_MMR0 interrupt request |
level |
| WKUP_CTRL_MMR0 |
WKUP_CTRL_MMR0_access_err_0 |
C7X256V0_CLEC_gic_spi_IN_129 |
C7X256V0_CLEC |
WKUP_CTRL_MMR0 interrupt request |
level |
| C7X256V1_CLEC_gic_spi_IN_129 |
C7X256V1_CLEC |
WKUP_CTRL_MMR0 interrupt request |
level |
| R5FSS0_CORE0_intr_IN_128 |
R5FSS0_CORE0 |
WKUP_CTRL_MMR0 interrupt request |
level |
| R5FSS0_CORE1_intr_IN_128 |
R5FSS0_CORE1 |
WKUP_CTRL_MMR0 interrupt request |
level |
| R5FSS1_CORE0_intr_IN_128 |
R5FSS1_CORE0 |
WKUP_CTRL_MMR0 interrupt request |
level |
| R5FSS1_CORE1_intr_IN_128 |
R5FSS1_CORE1 |
WKUP_CTRL_MMR0 interrupt request |
level |
| WKUP_R5FSS0_CORE0_intr_IN_128 |
WKUP_R5FSS0_CORE0 |
WKUP_CTRL_MMR0 interrupt request |
level |