SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Every asynchronous and control designates the first two bytes of each packet as the packet length. Each packet must be no more than 2048 bytes (packet length ≤ 2048).
Software must set the buffer ready bit (RDYn) for each buffer as it programs the DMA. As hardware processes each buffer, it sets the done bit (DNEn) and generates an interrupt. When hardware finishes the buffer processing, it can begin processing another buffer if RDYn is set. The application is responsible for setting up and configuring the channel buffer descriptor prior to every DMA access on the channel.
Two-packet modes are supported by hardware for programming the DMA. These are single-packet mode and multiple-packet mode.