SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The QSPI boot mode supports 1S-1S-4S mode only. The ROM issues a Read Command (0x6B) through the DAC interface of the controller followed by a 24 bit (3 byte) address (the starting address is all zeros) and then 8 dummy cycles. The flash device can then respond with 4-bit data from the starting address. The data reads linearly (and read commands possibly re-issued) until the end of the image has been reached. The frequency of operation supported is 50MHz.