Program Clock Zone 0 divider and Clock Zone 1 divider values (optional step, required if ASRC module dividers are being used):
ASRC_ICKDIV[13-0] CLOCK_ZONE0_DIVIDE
ASRC_ICKDIV[29-16] CLOCK_ZONE1_DIVIDE
ASRC_OCKDIV[13-0] CLOCK_ZONE0_DIVIDE
ASRC_OCKDIV[29-16] CLOCK_ZONE1_DIVIDE
Program Clock Zone 0 divider enable and Clock Zone 1 divider enable (optional step, required if ASRC module dividers are being used):
ASRC_ICKDIV[14] CLOCK_ZONE0_DIVIDE_EN
ASRC_ICKDIV[30] CLOCK_ZONE1_DIVIDE_EN
ASRC_OCKDIV[14] CLOCK_ZONE0_DIVIDE_EN
ASRC_OCKDIV[30] CLOCK_ZONE1_DIVIDE_EN
Program Input Group and Output Group Select Registers (select channels):
ASRC_IGRPSEL_0 to ASRC_IGRPSEL_3[...]
CHANNEL_#_GROUP_ENABLE
ASRC_OGRPSEL_0 to ASRC_OGRPSEL_3[...]
CHANNEL_#_GROUP_ENABLE
Program INFIFO threshold and OUTFIFO threshold values:
ASRC_GFFCTRL_0[7-0] INFIFO_THRESHOLD
ASRC_GFFCTRL_0[23-16] OUTFIFO_THRESHOLD
Program Output Word Length, Group Delay, De-emphasis Mode, Attenuation, Direct Down Sample, Mute, Dither Enable, Output Clock Zone Select and Input Clock Zone Select:
ASRC_GSRCCTRL_0[29-28] OUTPUT_WORD_LENGTH
ASRC_GSRCCTRL_0[27-26] GROUP_DELAY
ASRC_GSRCCTRL_0[25-24] DE_EMPHASIS_MODE
ASRC_GSRCCTRL_0[23-16] ATTENUATION
ASRC_GSRCCTRL_0[10] DIRECT_DOWN_SAMPLE
ASRC_GSRCCTRL_0[9] MUTE
ASRC_GSRCCTRL_0[8] DITHER_ENABLE
ASRC_GSRCCTRL_0[7-6] INPUT_WORD_LENGTH
ASRC_GSRCCTRL_0[5-3]
OUTPUT_CLOCK_ZONE_SELECT
ASRC_GSRCCTRL_0[2-0] INPUT_CLOCK_ZONE_SELECT
Program Data Alignment Disable:
ASRC_SYSCONFIG[1] DATA_FORMAT_DISABLE
Program Channel Enable (channel enable will be effective, only if that particular channel is the part of a that particular group):
ASRC_GSRCCTRL_0[31-30] CHANNEL_ENABLE
Program DMA transfers:
Once the INGROUP_EVT event is triggered, a
maximum block of ASRC_GFFCTRL_0[7-0] INFIFO_THRESHOLD audio samples can
be written to the data register of each channel of that group. Once the
OUTGROUP_EVT event is triggered, ASRC_GFFCTRL_0[23-16] OUTFIFO_THRESHOLD
samples can be read from OUTPUT FIFO DATA registers (ASRC_GOFDATAL_0 and
ASRC_GOFDATAR_0) of channel in the group. Events will not be triggered
until Input Clock Recovery Loop and Output Clock Recovery Loop are
settled. For this SW must check the status of bit [8] SETTLE in
ASRC_ICKZCTRL_0 and ASRC_OCKZCTRL_0 registers, respectively.