SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
IR-IrDA and IR-CIR modes only. MDR2[0] describes the status of the interrupt in IIR[5]. The IRTX_UNDERRUN bit should be read after an IIR[5] TX_STATUS_IT interrupt has occurred. The bits [2:1] of this register sets the trigger level for the frame status FIFO (8 entries) and must be programmed before the mode is programmed in MDR1[2:0]. Note: The MDR2[6] gives the flexibility to invert the RX pin inside the UART module to ensure that the protocol at the input of the transceiver module has the same polarity at module level. By default, the RX pin is inverted because most of transceiver invert the IR receive pin.
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 0024h |
| UART1 | 0281 0024h |
| UART2 | 0282 0024h |
| UART3 | 0283 0024h |
| UART4 | 0284 0024h |
| UART5 | 0285 0024h |
| UART6 | 0286 0024h |
| WKUP_UART0 | 2B30 0024h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_24 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| SET_TXIR_ALT | IRRXINVERT | CIR_PULSE_MODE | UART_PULSE | STS_FIFO_TRIG | IRTX_UNDERRUN | ||
| R/W | R/W | R/W | R/W | R/W | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED_24 | R | 0h | |
| 7 | SET_TXIR_ALT | R/W | 0h | Provide alternate functionnality for MDR1[4] [SET_TXIR] 0 Normal mode 1 Alternate mode for SET_TXIR |
| 6 | IRRXINVERT | R/W | 0h | Only for IR mode [IRDA & CIR]Invert RX pin inside the module before the voting or sampling system logic of the infra red block. This will not affect the RX path in UART Modem modes. 0 inversion is performed 1 No inversion is performed |
| 5:4 | CIR_PULSE_MODE | R/W | 0h | CIR Pulse modulation definition. It defines high level of the pulse width associated with a digit: 0 Pulse width of 3 from 12 cycles 1 Pulse width of 4 from 12 cycles 2 Pulse width of 5 from 12 cycles 3 Pulse width of 6 from 12 cycles |
| 3 | UART_PULSE | R/W | 0h | UART mode only. Used to allow pulse shaping in UART mode. 0 normal UART mode 1 UART mode with a pulse shaping |
| 2:1 | STS_FIFO_TRIG | R/W | 0h | Only for IR-IRDA mode.
Frame Status FIFO Threshold select: 0 1 entry 1 4 entries 2 7 entries 3 8 entries |
| 0 | IRTX_UNDERRUN | R | 0h | IRDA Transmission status interrupt.When the IIR[5] interrupt occurs, the meaning of the interrupt is : 0 the last bit of the frame has been
transmitted successfully without error.
1 an underrun has occurred. The last bit of
the frame has been transmitted but with an
underrun error present. The bit is reset to
'0' when the RESUME register is read. |