SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
The Interrupt Enable Set register is written by software to enable (i.e. unmask) specified bits to allow their current status to be considered in the generation of the corresponding level sensitive virtual interrupt output.
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| Instance Name | Physical Address |
|---|---|
| DMASS0_INTAGGR_0 | 4800 0000h + formula |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 48 |
| INTR_ENABLE | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
| INTR_ENABLE | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
| INTR_ENABLE | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| INTR_ENABLE | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| INTR_ENABLE | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INTR_ENABLE | |||||||
| R/W1TS | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:0 | INTR_ENABLE | R/W1TS | 0h | Interrupt enable set value. On writes, set bits will cause corresponding bits in the internal interrupt enable register to be set. Reads will reflect back the current status of the internal interrupt enable register. Reset Source: srst_n |