SPRUJC6A December 2024 ā July 2025 AM2752-Q1 , AM2754-Q1
If the requests are configured in DMA, write_count and read_count are assigned with āNā when the DMA handlers have completed their āNā CBASS0 accesses.
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Start the channel | MCSPI_CH(i)CTRL[0] EN | 1 |
| Wait for write_count = N AND read_count = N | ||
| Stop the channel | MCSPI_CH(i)CTRL[0] EN | 0 |
| Step | Register/Bit Field/Programming Model | Value |
|---|---|---|
| Read MCSPI_IRQSTATUS | MCSPI_IRQSTATUS | 0x- |
| Write MCSPI_IRQSTATUS to reset channel status bits | MCSPI_IRQSTATUS[channel i bits] | 0b1111 |
| IF: TXi_EMPTY | ||
| Write the transmitter register with data | MCSPI_TXi | 0x- |
| Increment write_count +1 | ||
| IF: RXi_FULL | ||
| Read the receiver register | MCSPI_RXi | |
| Increment read_count +1 | ||
| ENDIF | ||