SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 042Ch + formula |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_31_14 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_31_14 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_31_14 | HIRDD | L1_TIMEOUT | |||||
| R | R/W | R/W | |||||
| 0h | 0h | 0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| L1_TIMEOUT | HIRDM | ||||||
| R/W | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:14 | RESERVED_31_14 | R | 0h | Reserved For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. |
| 13:10 | HIRDD | R/W | 0h | PORTHLPMC_20 HIRDD Reset Source: rst_mod_g_rst_n |
| 9:2 | L1_TIMEOUT | R/W | 0h | PORTHLPMC_20 L1_TIMEOUT. For a description of this standard USB register field, see the eXtensible Host Controller Interface for Universal Serial Bus [USB] Specification 3.0. Reset Source: rst_mod_g_rst_n |
| 1:0 | HIRDM | R/W | 0h | Host Initiated Resume Duration Mode [HIRDM] - RWS. Default = 0h. Indicates which HIRD value must be used. The following are permissible values: Value Description 0 Initiate L1 using HIRD only on timeout. [default] 1 Initiate L1 using HIRDD on timeout. If rejected by device, initiate L1 using HIRD. 3-2 Reserved. Reset Source: rst_mod_g_rst_n |