SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Selects the clock source for USART3 functional clock
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| MAIN_CTRL_MMR0 | 0010 828Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | USART3_CLKSEL_CLK_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:1 | RESERVED | NONE | 0h | Reserved |
| 0 | USART3_CLKSEL_CLK_SEL | R/W | 0h | Selects the clock source for UART3: Field values (others are reserved): 1'b0 - MAIN_PLL1_HSDIV0_CLKOUT Divider Output (See USART3_CLK_CTRL) 1'b1 - MAIN_PLL1_HSDIV1_CLKOUT Reset Source: mod_g_rst_n |