SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Contains the result of power-on self tests.
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4300 C2C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | POST_STAT_FPOST_PLL_LOCK_TIMEOUT | POST_STAT_FPOST_PLL_LOCKLOSS | |||||
| NONE | R | R | |||||
| 0h | 0h | 0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| POST_STAT_POST_PBIST_FAIL | RESERVED | POST_STAT_POST_PBIST_TIMEOUT | POST_STAT_POST_PBIST_DONE | ||||
| R | NONE | R | R | ||||
| 0h | 0h | 0h | 0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | NONE | 0h | Reserved |
| 17 | POST_STAT_FPOST_PLL_LOCK_TIMEOUT | R | 0h | Differentiates between Fast POST and Slow POST. Fast POST is initiated after the PLL locks using the settings in the POST_CFG MMR. Otherwise, if the PLL lock times out, Slow POST is initated at the PLL reference clock rate. Field values (others are reserved): 1'b0 - FAST_POST 1'b1 - SLOW_POST Reset Source: mod_por_rst_n |
| 16 | POST_STAT_FPOST_PLL_LOCKLOSS | R | 0h | Indicates that POST exited with a PLL Lockloss Error Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - EXITED_ON_LOCK_LOSS Reset Source: mod_por_rst_n |
| 15 | POST_STAT_POST_PBIST_FAIL | R | 0h | POST PBIST failed Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - FAIL Reset Source: mod_por_rst_n |
| 14:10 | RESERVED | NONE | 0h | Reserved |
| 9 | POST_STAT_POST_PBIST_TIMEOUT | R | 0h | POST PBIST timed out Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - TIMEOUT Reset Source: mod_por_rst_n |
| 8 | POST_STAT_POST_PBIST_DONE | R | 0h | POST PBIST done Field values (others are reserved): 1'b0 - UNKNOWN 1'b1 - DONE Reset Source: mod_por_rst_n |
| 7:0 | RESERVED | NONE | 0h | Reserved |