SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register is dedicated to enable the channel 0
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| Instance Name | Physical Address |
|---|---|
| MCSPI0 | 2010 0134h |
| MCSPI1 | 2011 0134h |
| MCSPI2 | 2012 0134h |
| MCSPI3 | 2013 0134h |
| MCSPI4 | 2014 0134h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED_2 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED_2 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| EXTCLK | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED_1 | EN | ||||||
| R | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | RESERVED_2 | R | 0h | Read returns 0 |
| 15:8 | EXTCLK | R/W | 0h | Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle [MCSPI_CHCONF[CLKG] set to 1] Then the max value reached is 4096 clock divider ratio 0 Clock ratio is CLKD + 1. 1 Clock ratio is CLKD + 1 + 16. FF Clock ratio is CLKD + 1 + 4080. |
| 7:1 | RESERVED_1 | R | 0h | Read returns 0 |
| 0 | EN | R/W | 0h | Channel Enable 0 Channel i is not active. 1 Channel i is active. |