The PDMA5 - ADC module supports the following features:
- Implements CPPI 5.0 compliant Third Party Unified Transfer Controller
- Provides 0 memory write access unit(s)
- Each unit supports write bursts up to 64 bytes (on selected channel types)
- Provides 1 memory read access unit(s)
- Supports 1 outstanding read per interface (VBUSP).
- Supports read burst up to 64 bytes (on selected channel types)
- Read Unit 0:
- Provides a 32 bit wide VBUSP read only master interface for peripheral accesses.
- Supports up to 0 simultaneous destination (Tx) channels
- Supports negative credit monitoring on Tx channels
- Supports up to 2 simultaneous source (Rx) channels
- Supports Static Transfer Requests Only
- Supports X-Y, MCAN, and AASRC transfer modes (as per configuration)
- Provides per-channel buffering:
- Provides 8 128-bit word deep data FIFO for each destination channel
- Provides 8 128-bit word deep data FIFO for each source channel
- Provides 128 bit wide PSI-L compliant data interface to remote paired DMA and remote peripherals
- Provides 128 bit wide PSI-L compliant data interface from remote paired DMA and remote peripherals
The module does not support the following:
- Dynamic Transfer Request
- Cross Channel Triggering