SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Global Status Register
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| Instance Name | Physical Address |
|---|---|
| USB0 | 3100 C118h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| CBELT | |||||||
| R | |||||||
| 7E8h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CBELT | RESERVED_19_12 | ||||||
| R | R | ||||||
| 7E8h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED_19_12 | SSIC_IP | OTG_IP | BC_IP | ADP_IP | |||
| R | R | R | R | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| HOST_IP | DEVICE_IP | CSRTIMEOUT | BUSERRADDRVLD | RESERVED_3_2 | CURMOD | ||
| R | R | R/W1TC | R/W1TC | R | R | ||
| 0h | 0h | 0h | 0h | 0h | 0h | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | CBELT | R | 7E8h | Current BELT Value In Host mode, this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command. Reset Source: rst_mod_g_rst_n |
| 19:12 | RESERVED_19_12 | R | 0h | Reserved |
| 11 | SSIC_IP | R | 0h | This field is not used. Reset Source: rst_mod_g_rst_n |
| 10 | OTG_IP | R | 0h | This field is not used. Reset Source: rst_mod_g_rst_n |
| 9 | BC_IP | R | 0h | Battery Charger Interrupt Pending This field indicates that there is a pending interrupt pertaining to BC in BCEVT register. Reset Source: rst_mod_g_rst_n |
| 8 | ADP_IP | R | 0h | This field is not used. Reset Source: rst_mod_g_rst_n |
| 7 | HOST_IP | R | 0h | Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue. Reset Source: rst_mod_g_rst_n |
| 6 | DEVICE_IP | R | 0h | Device Interrupt Pending This field indicates that there is a pending interrupt pertaining to peripheral [device] operation in the Device event queue. Reset Source: rst_mod_g_rst_n |
| 5 | CSRTIMEOUT | R/W1TC | 0h | CSR Timeout When this bit is 1'b1, it indicates that the software performed a write or read to a controller register that could not be completed within DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles [default: h1FFFF]. Reset Source: rst_mod_g_rst_n |
| 4 | BUSERRADDRVLD | R/W1TC | 0h | Bus Error Address Valid [BusErrAddrVld] Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error. Note: Only supported in AHB and AXI configurations. Reset Source: rst_mod_g_rst_n |
| 3:2 | RESERVED_3_2 | R | 0h | Reserved |
| 1:0 | CURMOD | R | 0h | Current Mode of Operation [CurMod] Indicates the current mode of operation: - 2'b00: Device mode - 2'b01: Host mode Reset Source: rst_mod_g_rst_n |