SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
C7x core can access 6MB on-chip SRAM using two sets of addresses, one set address starting at 0x7200 0000 and the second address starting 0x8000 0000. When C7x access the on-chip SRAM using the address range between 0x7200 0000 to 0x725F FFFF, L1D only supports write through capability. When C7x access the on-chip SRAM using address range between 0x8000 0000 to 0x805F FFFF, the L1D cache write back feature can be supported. DRU inside C7x and the streaming engine for C7x can also use both address ranges to access on-chip SRAM.
For all the other initiators in SoC such as Pulsar R5F, DMSS, USB, EMMC, DAP and etc, the on-chip SRAM can only be accessed using address 0x7200 0000 to 0x725F FFFF. Any access to address range 0x8000 0000 to 0x805F FFFF from initiators other than C7x core, DRU inside C7x, and streaming engine inside C7x, can cause a transaction error.
The below table summarizes the different addresses needed for C7x access to SRAM.| Region Name | L1D Cache Address | All Other Initiators | Size |
|---|---|---|---|
| MSRAM_1MB0_RAM | 0x8000 0000 | 0x7200 0000 | 1MB |
| MSRAM_1MB1_RAM | 0x8010 0000 | 0x7210 0000 | 1MB |
| MSRAM_1MB2_RAM | 0x8020 0000 | 0x7220 0000 | 1MB |
| MSRAM_1MB3_RAM | 0x8030 0000 | 0x7230 0000 | 1MB |
| MSRAM_1MB4_RAM | 0x8040 0000 | 0x7240 0000 | 1MB |
| MSRAM_1MB5_RAM | 0x8050 0000 | 0x7250 0000 | 1MB |