| MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_0 |
PDMA0_spi_main_0_rx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_1 |
PDMA0_spi_main_0_rx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_2 |
PDMA0_spi_main_0_rx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_read_event_3 |
PDMA0_spi_main_0_rx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_0 |
PDMA0_spi_main_0_tx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_1 |
PDMA0_spi_main_0_tx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_2 |
PDMA0_spi_main_0_tx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_IN_0 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_IN_1 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_IN_2 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_dma_write_event_3 |
PDMA0_spi_main_0_tx_IN_3 |
PDMA0 |
MCSPI0 interrupt request |
pulse |
| MCSPI0 |
MCSPI0_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_204 |
C7X256V0_CLEC |
MCSPI0 interrupt request |
level |
| MCSPI0 |
MCSPI0_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_204 |
C7X256V1_CLEC |
MCSPI0 interrupt request |
level |
| MCSPI0 |
MCSPI0_intr_spi_0 |
R5FSS0_CORE0_intr_IN_204 |
R5FSS0_CORE0 |
MCSPI0 interrupt request |
level |
| MCSPI0 |
MCSPI0_intr_spi_0 |
R5FSS0_CORE1_intr_IN_204 |
R5FSS0_CORE1 |
MCSPI0 interrupt request |
level |
| MCSPI0 |
MCSPI0_intr_spi_0 |
R5FSS1_CORE0_intr_IN_204 |
R5FSS1_CORE0 |
MCSPI0 interrupt request |
level |
| MCSPI0 |
MCSPI0_intr_spi_0 |
R5FSS1_CORE1_intr_IN_204 |
R5FSS1_CORE1 |
MCSPI0 interrupt request |
level |
| MCSPI0 |
MCSPI0_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_204 |
WKUP_R5FSS0_CORE0 |
MCSPI0 interrupt request |
level |
| MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_0 |
PDMA0_spi_main_1_rx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_1 |
PDMA0_spi_main_1_rx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_2 |
PDMA0_spi_main_1_rx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_read_event_3 |
PDMA0_spi_main_1_rx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_0 |
PDMA0_spi_main_1_tx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_1 |
PDMA0_spi_main_1_tx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_2 |
PDMA0_spi_main_1_tx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_IN_0 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_IN_1 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_IN_2 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_dma_write_event_3 |
PDMA0_spi_main_1_tx_IN_3 |
PDMA0 |
MCSPI1 interrupt request |
pulse |
| MCSPI1 |
MCSPI1_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_205 |
C7X256V0_CLEC |
MCSPI1 interrupt request |
level |
| MCSPI1 |
MCSPI1_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_205 |
C7X256V1_CLEC |
MCSPI1 interrupt request |
level |
| MCSPI1 |
MCSPI1_intr_spi_0 |
R5FSS0_CORE0_intr_IN_205 |
R5FSS0_CORE0 |
MCSPI1 interrupt request |
level |
| MCSPI1 |
MCSPI1_intr_spi_0 |
R5FSS0_CORE1_intr_IN_205 |
R5FSS0_CORE1 |
MCSPI1 interrupt request |
level |
| MCSPI1 |
MCSPI1_intr_spi_0 |
R5FSS1_CORE0_intr_IN_205 |
R5FSS1_CORE0 |
MCSPI1 interrupt request |
level |
| MCSPI1 |
MCSPI1_intr_spi_0 |
R5FSS1_CORE1_intr_IN_205 |
R5FSS1_CORE1 |
MCSPI1 interrupt request |
level |
| MCSPI1 |
MCSPI1_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_205 |
WKUP_R5FSS0_CORE0 |
MCSPI1 interrupt request |
level |
| MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_0 |
PDMA0_spi_main_2_rx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_1 |
PDMA0_spi_main_2_rx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_2 |
PDMA0_spi_main_2_rx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_read_event_3 |
PDMA0_spi_main_2_rx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_0 |
PDMA0_spi_main_2_tx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_1 |
PDMA0_spi_main_2_tx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_2 |
PDMA0_spi_main_2_tx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_IN_0 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_IN_1 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_IN_2 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_dma_write_event_3 |
PDMA0_spi_main_2_tx_IN_3 |
PDMA0 |
MCSPI2 interrupt request |
pulse |
| MCSPI2 |
MCSPI2_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_206 |
C7X256V0_CLEC |
MCSPI2 interrupt request |
level |
| MCSPI2 |
MCSPI2_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_206 |
C7X256V1_CLEC |
MCSPI2 interrupt request |
level |
| MCSPI2 |
MCSPI2_intr_spi_0 |
R5FSS0_CORE0_intr_IN_206 |
R5FSS0_CORE0 |
MCSPI2 interrupt request |
level |
| MCSPI2 |
MCSPI2_intr_spi_0 |
R5FSS0_CORE1_intr_IN_206 |
R5FSS0_CORE1 |
MCSPI2 interrupt request |
level |
| MCSPI2 |
MCSPI2_intr_spi_0 |
R5FSS1_CORE0_intr_IN_206 |
R5FSS1_CORE0 |
MCSPI2 interrupt request |
level |
| MCSPI2 |
MCSPI2_intr_spi_0 |
R5FSS1_CORE1_intr_IN_206 |
R5FSS1_CORE1 |
MCSPI2 interrupt request |
level |
| MCSPI2 |
MCSPI2_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_206 |
WKUP_R5FSS0_CORE0 |
MCSPI2 interrupt request |
level |
| MCSPI3 |
MCSPI3_dma_read_event_0 |
PDMA4_spi_main_3_rx_IN_0 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_0 |
PDMA4_spi_main_3_rx_IN_1 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_0 |
PDMA4_spi_main_3_rx_IN_2 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_0 |
PDMA4_spi_main_3_rx_IN_3 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_1 |
PDMA4_spi_main_3_rx_IN_0 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_1 |
PDMA4_spi_main_3_rx_IN_1 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_1 |
PDMA4_spi_main_3_rx_IN_2 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_1 |
PDMA4_spi_main_3_rx_IN_3 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_2 |
PDMA4_spi_main_3_rx_IN_0 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_2 |
PDMA4_spi_main_3_rx_IN_1 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_2 |
PDMA4_spi_main_3_rx_IN_2 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_2 |
PDMA4_spi_main_3_rx_IN_3 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_3 |
PDMA4_spi_main_3_rx_IN_0 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_3 |
PDMA4_spi_main_3_rx_IN_1 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_3 |
PDMA4_spi_main_3_rx_IN_2 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_read_event_3 |
PDMA4_spi_main_3_rx_IN_3 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_0 |
PDMA4_spi_main_3_tx_IN_0 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_0 |
PDMA4_spi_main_3_tx_IN_1 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_0 |
PDMA4_spi_main_3_tx_IN_2 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_0 |
PDMA4_spi_main_3_tx_IN_3 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_1 |
PDMA4_spi_main_3_tx_IN_0 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_1 |
PDMA4_spi_main_3_tx_IN_1 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_1 |
PDMA4_spi_main_3_tx_IN_2 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_1 |
PDMA4_spi_main_3_tx_IN_3 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_2 |
PDMA4_spi_main_3_tx_IN_0 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_2 |
PDMA4_spi_main_3_tx_IN_1 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_2 |
PDMA4_spi_main_3_tx_IN_2 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_2 |
PDMA4_spi_main_3_tx_IN_3 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_3 |
PDMA4_spi_main_3_tx_IN_0 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_3 |
PDMA4_spi_main_3_tx_IN_1 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_3 |
PDMA4_spi_main_3_tx_IN_2 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_dma_write_event_3 |
PDMA4_spi_main_3_tx_IN_3 |
PDMA4 |
MCSPI3 interrupt request |
pulse |
| MCSPI3 |
MCSPI3_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_207 |
C7X256V0_CLEC |
MCSPI3 interrupt request |
level |
| MCSPI3 |
MCSPI3_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_207 |
C7X256V1_CLEC |
MCSPI3 interrupt request |
level |
| MCSPI3 |
MCSPI3_intr_spi_0 |
R5FSS0_CORE0_intr_IN_207 |
R5FSS0_CORE0 |
MCSPI3 interrupt request |
level |
| MCSPI3 |
MCSPI3_intr_spi_0 |
R5FSS0_CORE1_intr_IN_207 |
R5FSS0_CORE1 |
MCSPI3 interrupt request |
level |
| MCSPI3 |
MCSPI3_intr_spi_0 |
R5FSS1_CORE0_intr_IN_207 |
R5FSS1_CORE0 |
MCSPI3 interrupt request |
level |
| MCSPI3 |
MCSPI3_intr_spi_0 |
R5FSS1_CORE1_intr_IN_207 |
R5FSS1_CORE1 |
MCSPI3 interrupt request |
level |
| MCSPI3 |
MCSPI3_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_207 |
WKUP_R5FSS0_CORE0 |
MCSPI3 interrupt request |
level |
| MCSPI4 |
MCSPI4_dma_read_event_0 |
PDMA4_spi_main_4_rx_IN_0 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_0 |
PDMA4_spi_main_4_rx_IN_1 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_0 |
PDMA4_spi_main_4_rx_IN_2 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_0 |
PDMA4_spi_main_4_rx_IN_3 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_1 |
PDMA4_spi_main_4_rx_IN_0 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_1 |
PDMA4_spi_main_4_rx_IN_1 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_1 |
PDMA4_spi_main_4_rx_IN_2 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_1 |
PDMA4_spi_main_4_rx_IN_3 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_2 |
PDMA4_spi_main_4_rx_IN_0 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_2 |
PDMA4_spi_main_4_rx_IN_1 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_2 |
PDMA4_spi_main_4_rx_IN_2 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_2 |
PDMA4_spi_main_4_rx_IN_3 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_3 |
PDMA4_spi_main_4_rx_IN_0 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_3 |
PDMA4_spi_main_4_rx_IN_1 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_3 |
PDMA4_spi_main_4_rx_IN_2 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_read_event_3 |
PDMA4_spi_main_4_rx_IN_3 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_0 |
PDMA4_spi_main_4_tx_IN_0 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_0 |
PDMA4_spi_main_4_tx_IN_1 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_0 |
PDMA4_spi_main_4_tx_IN_2 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_0 |
PDMA4_spi_main_4_tx_IN_3 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_1 |
PDMA4_spi_main_4_tx_IN_0 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_1 |
PDMA4_spi_main_4_tx_IN_1 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_1 |
PDMA4_spi_main_4_tx_IN_2 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_1 |
PDMA4_spi_main_4_tx_IN_3 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_2 |
PDMA4_spi_main_4_tx_IN_0 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_2 |
PDMA4_spi_main_4_tx_IN_1 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_2 |
PDMA4_spi_main_4_tx_IN_2 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_2 |
PDMA4_spi_main_4_tx_IN_3 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_3 |
PDMA4_spi_main_4_tx_IN_0 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_3 |
PDMA4_spi_main_4_tx_IN_1 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_3 |
PDMA4_spi_main_4_tx_IN_2 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_dma_write_event_3 |
PDMA4_spi_main_4_tx_IN_3 |
PDMA4 |
MCSPI4 interrupt request |
pulse |
| MCSPI4 |
MCSPI4_intr_spi_0 |
C7X256V0_CLEC_gic_spi_IN_208 |
C7X256V0_CLEC |
MCSPI4 interrupt request |
level |
| MCSPI4 |
MCSPI4_intr_spi_0 |
C7X256V1_CLEC_gic_spi_IN_208 |
C7X256V1_CLEC |
MCSPI4 interrupt request |
level |
| MCSPI4 |
MCSPI4_intr_spi_0 |
R5FSS0_CORE0_intr_IN_208 |
R5FSS0_CORE0 |
MCSPI4 interrupt request |
level |
| MCSPI4 |
MCSPI4_intr_spi_0 |
R5FSS0_CORE1_intr_IN_208 |
R5FSS0_CORE1 |
MCSPI4 interrupt request |
level |
| MCSPI4 |
MCSPI4_intr_spi_0 |
R5FSS1_CORE0_intr_IN_208 |
R5FSS1_CORE0 |
MCSPI4 interrupt request |
level |
| MCSPI4 |
MCSPI4_intr_spi_0 |
R5FSS1_CORE1_intr_IN_208 |
R5FSS1_CORE1 |
MCSPI4 interrupt request |
level |
| MCSPI4 |
MCSPI4_intr_spi_0 |
WKUP_R5FSS0_CORE0_intr_IN_208 |
WKUP_R5FSS0_CORE0 |
MCSPI4 interrupt request |
level |