SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
<PLL_Name>_HSDIV_CTRLk[15] CLKOUT_EN = 0 cleanly disables the HSDIV output clock
<PLL_Name>_HSDIV_CTRLk[6-0] HSDIV = <value> for divider
<PLL_Name>_HSDIV_CTRLk[8] SYNC_DIS = 0 insures that the divider changes occur synchronously to the internal divider of the HSDIV block.
when the clock is required,
<PLL_Name>_HSDIV_CTRLk[15] CLKOUT_EN = 1 cleanly enables the HSDIV output clock