SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
This register contains the enable interrupt status as defined in HL0.8 for the Input Group interrupts. The FIFO interrupt for each group is configured in the control register for the group. A read of the Interrupt Enable Clr register returns the current enable bits for the interrupt sources. A write to this register sets the enable to 0 for any source whose corresponding bit is 1 in the value written
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| Instance Name | Physical Address |
|---|---|
| AASRC0 | 02D0 0050h |
| AASRC1 | 02D4 0050h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GROUP_3_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR | GROUP_2_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR | GROUP_1_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR | GROUP_0_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR | |||
| R | R/W1TC | R/W1TC | R/W1TC | R/W1TC | |||
| 0h | 0h | 0h | 0h | 0h | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:4 | RESERVED | R | 0h | Always read as 0 |
| 3 | GROUP_3_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Group 3 Input FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 2 | GROUP_2_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Group 2 Input FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 1 | GROUP_1_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Group 1 Input FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |
| 0 | GROUP_0_INPUT_FIFO_THRESHOLD_ENABLE_CLEAR | R/W1TC | 0h | Group 0 Input FIFO Threshold Interrupt Read indicates interrupt enable. Writing 1 will clear enable and Writing 0 has no effect 0 Interrupt is not enabled 1 Interrupt is enabled |