SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Component interrupt request enable Write 1 to set;enable interrupt. Readout equal to corresponding _CLR register.
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| Instance Name | Physical Address |
|---|---|
| TIMER0 | 0240 002Ch |
| TIMER1 | 0241 002Ch |
| TIMER2 | 0242 002Ch |
| TIMER3 | 0243 002Ch |
| TIMER4 | 0244 002Ch |
| TIMER5 | 0245 002Ch |
| TIMER6 | 0246 002Ch |
| TIMER7 | 0247 002Ch |
| TIMER8 | 0248 002Ch |
| TIMER9 | 0249 002Ch |
| TIMER10 | 024A 002Ch |
| TIMER11 | 024B 002Ch |
| TIMER12 | 024C 002Ch |
| TIMER13 | 024D 002Ch |
| TIMER14 | 024E 002Ch |
| TIMER15 | 024F 002Ch |
| WKUP_TIMER0 | 2B10 002Ch |
| WKUP_TIMER1 | 2B11 002Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TCAR_IT_FLAG | OVF_IT_FLAG | MAT_IT_FLAG | ||||
| NONE | R/W1TS | R/W1TS | R/W1TS | ||||
| 0h | 0h | 0h | 0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:3 | RESERVED | NONE | 0h | Reserved |
| 2 | TCAR_IT_FLAG | R/W1TS | 0h | Capture Interrupt Reset Source: mod_g_rst_n |
| 1 | OVF_IT_FLAG | R/W1TS | 0h | Overflow Interrupt Reset Source: mod_g_rst_n |
| 0 | MAT_IT_FLAG | R/W1TS | 0h | Match Interrupt Reset Source: mod_g_rst_n |