SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
A total of 2 destination channels are provided within the DMA for concurrent transfers from Tx per channel buffers to the various attached peripherals. Each Tx channel requires a single PSI-L thread. The Tx channels are allocated as follows:
| Tx DMA Channel | Function | Channel Type | Trigger Mode | Data FIFO Address | Strobe MMR Address | Control FIFO Address |
|---|---|---|---|---|---|---|
| 8000 | McASP 3 Tx Ch 0 | XY | edge | 000002B38000 | 000000000000 | 000000000000 |
| 8001 | McASP 4 Tx Ch 0 | XY | edge | 000002B48000 | 000000000000 | 000000000000 |