SPRUJC6A December 2024 – July 2025 AM2752-Q1 , AM2754-Q1
Smartcard (ISO7816) mode Control Register
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| Instance Name | Physical Address |
|---|---|
| UART0 | 0280 00A0h |
| UART1 | 0281 00A0h |
| UART2 | 0282 00A0h |
| UART3 | 0283 00A0h |
| UART4 | 0284 00A0h |
| UART5 | 0285 00A0h |
| UART6 | 0286 00A0h |
| WKUP_UART0 | 2B30 00A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED1 | |||||||
| R | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DSNACK | INACK | RESERVED | MAX_ITERATION | ||||
| R/W | R/W | R | R/W | ||||
| 0h | 0h | 0h | 7h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:8 | RESERVED1 | R | 0h | |
| 7 | DSNACK | R/W | 0h | Applies Max_Iteration to receiver aswell - when maximum number of NACKs have been returned, the receiver will accept the data regardless of error. The data will be loaded into the receiver FIFO and PE will be set when Reading it. Reset Source: mod_g_arstn |
| 6 | INACK | R/W | 0h | Inhibit NACK when receiving, even if an error is received. The data will be loaded into the receiver FIFO and PE will be set when Reading it. Reset Source: mod_g_arstn |
| 5:3 | RESERVED | R | 0h | |
| 2:0 | MAX_ITERATION | R/W | 7h | Number of times to repeat transmitted character, if the receiver did not acknowledge. If not acknowledged after the max value is reached, the USART transmitter will set parity error, stop and not continue until it is cleared. Reset Source: mod_g_arstn |